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EP1005166
European procedure
Extract from the Register of European Patents
EP About this file: EP1005166
| EP1005166 - Method for detecting frequency of digital phase locked loop [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 23.12.2005 Database last updated on 08.10.2024 | Most recent event Tooltip | 23.12.2005 | No opposition filed within time limit | published on 08.02.2006 [2006/06] | Applicant(s) | For all designated states Samsung Electronics Co., Ltd. 416, Maetan-dong Paldal-gu Suwon-City, Kyungki-do / KR | [N/P] |
| Former [2000/22] | For all designated states SAMSUNG ELECTRONICS CO., LTD. 416, Maetan-dong, Paldal-gu Suwon-City, Kyungki-do / KR | Inventor(s) | 01 /
Park, Hyun-Soo, 119-312, Hanshin Apt. 55-10, Jamwon dong, Seocho-gu Seoul / KR | 02 /
Shim, Jae-Seong 229-24, Jayang 1-dong, Kwangjin-gu Seoul / KR | 03 /
Won, Yong-Kwang 187, Shin 1-ri, Dongtan-myeon, Hwasung kun Kyungkido / KR | [2000/22] | Representative(s) | Chugg, David John, et al Appleyard Lees 15 Clare Road Halifax West Yorkshire HX1 2HY / GB | [N/P] |
| Former [2000/22] | Chugg, David John, et al Appleyard Lees, 15 Clare Road Halifax, West Yorkshire HX1 2HY / GB | Application number, filing date | 99309397.0 | 24.11.1999 | [2000/22] | Priority number, date | KR19980050947 | 26.11.1998 Original published format: KR 9850947 | [2000/22] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1005166 | Date: | 31.05.2000 | Language: | EN | [2000/22] | Type: | A3 Search report | No.: | EP1005166 | Date: | 15.01.2003 | [2003/03] | Type: | B1 Patent specification | No.: | EP1005166 | Date: | 16.02.2005 | Language: | EN | [2005/07] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.12.2002 | Classification | IPC: | H03L7/113, G01R23/02 | [2000/22] | CPC: |
H03L7/091 (EP,US);
H03L7/10 (KR);
G11B20/1403 (EP,US);
H03L7/113 (EP,US);
G01R23/10 (EP,US)
| Designated contracting states | DE, FR, GB, NL [2003/40] |
| Former [2000/22] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Verfahren zur Erfassung der Frequenz in einem digitalen Phasenregelkreis | [2000/22] | English: | Method for detecting frequency of digital phase locked loop | [2000/22] | French: | Procédé de détection de fréquence dans une boucle à verrouillage de phase numérique | [2000/22] | Examination procedure | 06.12.1999 | Examination requested [2000/22] | 06.03.2003 | Despatch of a communication from the examining division (Time limit: M04) | 27.06.2003 | Reply to a communication from the examining division | 13.10.2003 | Despatch of a communication from the examining division (Time limit: M04) | 14.02.2004 | Reply to a communication from the examining division | 09.08.2004 | Communication of intention to grant the patent | 02.12.2004 | Fee for grant paid | 02.12.2004 | Fee for publishing/printing paid | Opposition(s) | 17.11.2005 | No opposition filed within time limit [2006/06] | Fees paid | Renewal fee | 06.11.2001 | Renewal fee patent year 03 | 07.11.2002 | Renewal fee patent year 04 | 31.10.2003 | Renewal fee patent year 05 | 20.10.2004 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0342736 (PHILIPS NV [NL]) [X] 1-5 * column 6, line 8 - column 8, line 58; figures 1A-E,2 *; | [X]EP0544358 (PHILIPS NV [NL]) [X] 1-5 * column 9, line 16 - column 9, line 38 * * column 7, line 5 - column 7, line 37; figure 3 * * column 1, line 24 - column 1, line 27 *; | [A]US5416809 (MASUDA SHOZO [JP], et al) [A] 1-5 * the whole document *; | [A]EP0853386 (PLESSEY SEMICONDUCTORS LTD [GB]) [A] 1-5 * the whole document *; | [A]US5841323 (FUJIMOTO KENSUKE [JP]) [A] 1-5* the whole document * |