EP1062576 - COMPREHENSIVE REDUNDANT LOAD ELIMINATION FOR ARCHITECTURES SUPPORTING CONTROL AND DATA SPECULATION [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 04.12.2015 Database last updated on 24.04.2024 | Most recent event Tooltip | 04.12.2015 | Application deemed to be withdrawn | published on 06.01.2016 [2016/01] | Applicant(s) | For all designated states Intel Corporation 2200 Mission College Boulevard Santa Clara, CA 95054 / US | [N/P] |
Former [2000/52] | For all designated states INTEL CORPORATION 2200 Mission College Boulevard Santa Clara, CA 95052 / US | Inventor(s) | 01 /
WU, Youfeng 3658 Bryant Street Palo Alto, CA 94306 / US | 02 /
LEE, Yong-Fong 7265 Sleepy Creek Drive San Jose, CA 95120 / US | [2000/52] | Representative(s) | HGF 8th Floor 140 London Wall London EC2Y 5DN / GB | [N/P] |
Former [2009/36] | Harrison Goddard Foote 40-43 Chancery Lane London WC2A 1JA / GB | ||
Former [2004/10] | Molyneaux, Martyn William, et al Harrison Goddard Foote 40-43 Chancery Lane London WC2A 1JA / GB | ||
Former [2001/36] | Molyneaux, Martyn William, et al Wildman, Harrold, Allen & Dixon 11th Floor, Tower 3, Clements Inn London WC2A 2AZ / GB | ||
Former [2000/52] | Molyneaux, Martyn William Langner Parry 52-54 High Holborn London WC1V 6RR / GB | Application number, filing date | 99909696.9 | 26.02.1999 | [2000/52] | WO1999US04433 | Priority number, date | US19980038755 | 11.03.1998 Original published format: US 38755 | [2000/52] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO9946677 | Date: | 16.09.1999 | Language: | EN | [1999/37] | Type: | A1 Application with search report | No.: | EP1062576 | Date: | 27.12.2000 | Language: | EN | The application published by WIPO in one of the EPO official languages on 16.09.1999 takes the place of the publication of the European patent application. | [2000/52] | Search report(s) | International search report - published on: | US | 16.09.1999 | (Supplementary) European search report - dispatched on: | EP | 10.07.2003 | Classification | IPC: | G06F9/45 | [2000/52] | CPC: |
G06F8/433 (EP,US);
G06F8/443 (EP,US);
G06F8/445 (EP,US);
G06F9/30181 (EP);
G06F9/383 (EP,US);
G06F9/384 (EP);
G06F9/3842 (EP,US)
(-)
| Designated contracting states | DE, FR, GB [2000/52] | Title | German: | AUSGEDEHNTE REDUNDIERENDE LADUNGSELIMINATION FÜR ARCHITEKTUREN WELCHE KONTROLLENUND DATENSPEKULATIONEN UNTERSTÜTZEN | [2000/52] | English: | COMPREHENSIVE REDUNDANT LOAD ELIMINATION FOR ARCHITECTURES SUPPORTING CONTROL AND DATA SPECULATION | [2000/52] | French: | ELIMINATION GLOBALE DE LA CHARGE REDONDANTE DESTINEE AUX ARCHITECTURES QUI PRENNENT EN CHARGE LES COMMANDES ET LES SUPPOSITIONS EN MATIERE DE DONNEES | [2000/52] | Entry into regional phase | 09.10.2000 | National basic fee paid | 09.10.2000 | Search fee paid | 09.10.2000 | Designation fee(s) paid | 09.10.2000 | Examination fee paid | Examination procedure | 04.10.1999 | Request for preliminary examination filed International Preliminary Examining Authority: US | 09.10.2000 | Examination requested [2001/01] | 20.08.2003 | Amendment by applicant (claims and/or description) | 03.04.2006 | Despatch of a communication from the examining division (Time limit: M04) | 28.07.2006 | Reply to a communication from the examining division | 13.03.2008 | Despatch of a communication from the examining division (Time limit: M04) | 23.07.2008 | Reply to a communication from the examining division | 19.03.2015 | Despatch of a communication from the examining division (Time limit: M04) | 30.07.2015 | Application deemed to be withdrawn, date of legal effect [2016/01] | 27.08.2015 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2016/01] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 03.04.2006 | Fees paid | Renewal fee | 02.02.2001 | Renewal fee patent year 03 | 25.02.2002 | Renewal fee patent year 04 | 25.02.2003 | Renewal fee patent year 05 | 23.02.2004 | Renewal fee patent year 06 | 22.02.2005 | Renewal fee patent year 07 | 27.02.2006 | Renewal fee patent year 08 | 27.02.2007 | Renewal fee patent year 09 | 25.02.2008 | Renewal fee patent year 10 | 13.02.2009 | Renewal fee patent year 11 | 16.02.2010 | Renewal fee patent year 12 | 15.02.2011 | Renewal fee patent year 13 | 15.02.2012 | Renewal fee patent year 14 | 12.02.2013 | Renewal fee patent year 15 | 12.02.2014 | Renewal fee patent year 16 | Penalty fee | Additional fee for renewal fee | 28.02.2015 | 17   M06   Not yet paid |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y] - GUPTA R, "Code optimization as a side effect of instruction scheduling", HIGH-PERFORMANCE COMPUTING, 1997. PROCEEDINGS. FOURTH INTERNATIONAL CONFERENCE ON BANGALORE, INDIA 18-21 DEC. 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19971218), ISBN 0-8186-8067-9, pages 370 - 377, XP010255718 [Y] 1,2,5,6,8-10 * abstract * * page 370, column R, line 20 - line 33 * * page 375, column L, line 4 - line 7 * * page 375, column L, line 23 - page 376, column L, line 12 * DOI: http://dx.doi.org/10.1109/HIPC.1997.634517 | [Y] - HILDUM D ET AL, "A LANGUAGE FOR SPECIFYING PROGRAM TRANSFORMATIONS", IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, IEEE INC. NEW YORK, US, (19900601), vol. 16, no. 6, ISSN 0098-5589, pages 630 - 638, XP000128951 [Y] 1,2,5,6,8-10 * the whole document * DOI: http://dx.doi.org/10.1109/32.55091 | [A] - MOREL E ET AL, "Global optimization by suppression of partial redundancies", COMMUNICATIONS OF THE ACM, USA, (197902), vol. 22, no. 2, ISSN 0001-0782, pages 96 - 103, XP002245509 [A] 3,4,7 * page 97, column L, line 12 - line 19 * * page 98, column R, line 37 - line 42 * * page 99, column L, line 28 - column R, line 21 * DOI: http://dx.doi.org/10.1145/359060.359069 | [A] - BODIK R ET AL, "ARRAY DATA FLOW ANALYSIS FOR LOAD-STORE OPTIMIZATIONS IN FINE-GRAIN ARCHITECTURES", INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, PLENUM PRESS, NEW YORK, US, (19961201), vol. 24, no. 6, ISSN 0885-7458, pages 481 - 512, XP000635513 [A] 1,5-7,10 * page 484, line 16 - page 486, line 1 * * page 508, line 1 - page 509, line 4 * | International search | [Y]US5526499 (BERNSTEIN DAVID [US], et al); | [Y]US5537620 (BRETERNITZ JR MAURICIO [US]); | [Y]US5542075 (EBCIOGLU MAHMUT K [US], et al); | [YP] - DIWAN A, MCKINLEY K S, MOSS J E B, "TYPE-BASED ALIAS ANALYSIS", PLDI ́09 : proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation ; June 15 - 20, 2009, Dublin, Ireland, ACM Press, New York, New York, USA, New York, New York, USA, (19980617), doi:10.1145/277652.277670, ISBN 978-1-60558-392-1, pages 106 - 117, XP002918898 DOI: http://dx.doi.org/10.1145/277652.277670 | [AP] - LO R., ET AL., "REGISTER PROMOTION BY SPARSE PARTIAL REDUNDANCY ELIMINATION OF LOADS AND STORES.", PLDI ́09 : proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation ; June 15 - 20, 2009, Dublin, Ireland, ACM Press, New York, New York, USA, New York, New York, USA, (19980601), vol. 33., no. 05., doi:10.1145/277652.277659, ISBN 978-1-60558-392-1, pages 26 - 37., XP002918899 DOI: http://dx.doi.org/10.1145/277652.277659 | [A] - ROGERS A, LI K, "SOFTWARE SUPPORT FOR SPECULATIVE LOADS", ASPLOS. PROCEEDINGS. INTERNATIONAL CONFERENCE ON ARCHITECTURALSUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS, NEW YORK, NY, US, US, (19921001), pages 38 - 50, XP002918900 | [A] - MAHLKE S. A., ET AL., "SENTINEL SCHEDULING: A MODEL FOR COMPILER-CONTROLLED SPECULATIVE EXECUTION.", ACM Transactions on Computer Systems (TOCS), Association for Computing Machinery, Inc., US, US, (19931101), vol. 11., no. 04., doi:10.1145/161541.159765, ISSN 0734-2071, pages 376 - 408., XP002918901 DOI: http://dx.doi.org/10.1145/161541.159765 | [A] - KATHAIL V, SCHLANSKER M, RAU B R, "HPL PLAYDOH ARCHITECTURE SPECIFICATION: VERSION 1.0", HP LABORATORIES TECHNICAL REPORT., XX, XX, XX, (19940201), pages 01 + 01A + 02 - 37 + 39, XP002918902 |