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Extract from the Register of European Patents

EP About this file: EP1149385

EP1149385 - IC TEST SOFTWARE SYSTEM FOR MAPPING LOGICAL FUNCTIONAL TEST DATA OF LOGIC INTEGRATED CIRCUITS TO PHYSICAL REPRESENTATION [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  20.01.2006
Database last updated on 05.10.2024
Most recent event   Tooltip28.03.2008Lapse of the patent in a contracting state
New state(s): IT, SE		published on 30.04.2008  [2008/18]
Applicant(s)For all designated states
FEI COMPANY
5350 NE Dawson Creek Drive
Hillsboro, Or 97124 / US
For all designated states
Texas Instruments Incorporated
7839 Churchill Way
Mail Station 3999
Dallas, Texas 75251 / US
[N/P]
Former [2004/50]For all designated states
FEI Company
5350 NE Dawson Creek Drive
Hillsboro, Or 97124 / US
For all designated states
Texas Instruments Incorporated
7839 Churchill Way, Mail Station 3999
Dallas, Texas 75251 / US
Former [2002/10]For all designated states
Electroglas, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138 / US
For all designated states
Texas Instruments Incorporated
7839 Churchill Way, Mail Station 3999
Dallas, Texas 75251 / US
Former [2001/44]For all designated states
KNIGHTS TECHNOLOGY, INC
155 North Wolf Road
Sunnyvale, CA 94086 / US
For all designated states
Texas Instruments Incorporated
7839 Churchill Way, Mail Station 3999
Dallas, Texas 75251 / US
Inventor(s)01 / SMITH, Shawn
2001 South Mopac, Apartment 2436
Austin, TX 75746 / US
02 / BALACHANDRAN, Hari
7432 Frankfort Road, Apartment 212
Dallas, TX 75252 / US
03 / PARKER, Jason
307 Pinyon Lane
Coppell, TX 75019 / US
04 / WATTS BUTLER, Stephanie
4700 Winter Park Drive
Richardson, TX 75082 / US
 [2001/44]
Representative(s)Lomas, Geoffrey Michael, et al
Barker Brettell LLP Medina Chambers Town Quay Southampton
SO14 2AQ / GB
[N/P]
Former [2001/44]Lomas, Geoffrey Michael, et al
Barker Brettell Medina Chambers, Town Quay
Southampton SO14 2AQ / GB
Application number, filing date99958909.612.11.1999
[2001/44]
WO1999US26735
Priority number, dateUS1998019216413.11.1998         Original published format: US 192164
[2001/44]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO0030119
Date:25.05.2000
Language:EN
[2000/21]
Type: A1 Application with search report 
No.:EP1149385
Date:31.10.2001
Language:EN
The application published by WIPO in one of the EPO official languages on 25.05.2000 takes the place of the publication of the European patent application.
[2001/44]
Type: B1 Patent specification 
No.:EP1149385
Date:16.03.2005
Language:EN
[2005/11]
Search report(s)International search report - published on:US25.05.2000
(Supplementary) European search report - dispatched on:EP17.12.2001
ClassificationIPC:G11C29/00, G01R31/28, G01R31/3183
[2002/05]
CPC:
G01R31/318307 (EP,US); G01R31/2834 (EP,US)
Former IPC [2001/44]G11C29/00, G01R31/28
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE [2001/44]
TitleGerman:IC-TEST PROGRAMMIERSYSTEM ZUR ZUORDNUNG LOGISCHER FUNKTIONSTESTDATEN VON LOGISCHEN INTEGRIERTEN SCHALTUNG ZU EINER PHYSIKALISCHEN DARSTELLUNG[2001/44]
English:IC TEST SOFTWARE SYSTEM FOR MAPPING LOGICAL FUNCTIONAL TEST DATA OF LOGIC INTEGRATED CIRCUITS TO PHYSICAL REPRESENTATION[2001/44]
French:SYSTEME LOGICIEL D'ESSAI DE CIRCUIT INTEGRE DESTINE A FAIRE CORRESPONDRE DES DONNEES D'ESSAI FONCTIONNELLES LOGIQUES DE CIRCUITS INTEGRES LOGIQUES AVEC UNE REPRESENTATION PHYSIQUE[2001/44]
Entry into regional phase07.06.2001National basic fee paid 
07.06.2001Search fee paid 
07.06.2001Designation fee(s) paid 
07.06.2001Examination fee paid 
Examination procedure02.06.2000Request for preliminary examination filed
International Preliminary Examining Authority: US
07.06.2001Examination requested  [2001/44]
25.10.2002Despatch of a communication from the examining division (Time limit: M06)
22.04.2003Reply to a communication from the examining division
04.05.2004Communication of intention to grant the patent
13.08.2004Fee for grant paid
13.08.2004Fee for publishing/printing paid
Opposition(s)19.12.2005No opposition filed within time limit [2006/10]
Fees paidRenewal fee
02.11.2001Renewal fee patent year 03
27.11.2002Renewal fee patent year 04
21.11.2003Renewal fee patent year 05
22.11.2004Renewal fee patent year 06
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT16.03.2005
BE16.03.2005
CH16.03.2005
FI16.03.2005
IT16.03.2005
LI16.03.2005
NL16.03.2005
DK16.06.2005
GR16.06.2005
SE16.06.2005
ES27.06.2005
PT07.09.2005
CY12.11.2005
IE14.11.2005
LU30.11.2005
MC30.11.2005
[2008/18]
Former [2007/23]AT16.03.2005
BE16.03.2005
CH16.03.2005
FI16.03.2005
LI16.03.2005
NL16.03.2005
DK16.06.2005
GR16.06.2005
ES27.06.2005
PT07.09.2005
CY12.11.2005
IE14.11.2005
LU30.11.2005
MC30.11.2005
Former [2006/49]AT16.03.2005
BE16.03.2005
CH16.03.2005
FI16.03.2005
LI16.03.2005
NL16.03.2005
DK16.06.2005
GR16.06.2005
ES27.06.2005
PT07.09.2005
IE14.11.2005
MC30.11.2005
Former [2006/30]AT16.03.2005
BE16.03.2005
CH16.03.2005
FI16.03.2005
LI16.03.2005
NL16.03.2005
DK16.06.2005
GR16.06.2005
ES27.06.2005
PT07.09.2005
MC30.11.2005
Former [2006/14]AT16.03.2005
BE16.03.2005
CH16.03.2005
FI16.03.2005
LI16.03.2005
NL16.03.2005
DK16.06.2005
GR16.06.2005
ES27.06.2005
PT07.09.2005
Former [2006/12]AT16.03.2005
BE16.03.2005
CH16.03.2005
FI16.03.2005
LI16.03.2005
DK16.06.2005
Former [2005/51]AT16.03.2005
BE16.03.2005
FI16.03.2005
Former [2005/46]FI16.03.2005
Documents cited:Search[X]US5475695  (CAYWOOD JOHN M [US], et al) [X] 1-9 * column 2, line 37 - column 6, line 14; figures 1,2 *;
 [A]US5668745  (DAY CHRIS [US]) [A] 1-9 * column 3, line 18 - column 7, line 33; figures 2-5 *;
 [A]US5771243  (LEE ROBERT G-H [TW], et al) [A] 1-9* column 3, line 45 - column 4, line 59; figures 1-3 *
International search[Y]US4801869  (SPROGIS EDMUND J [US]);
 [X]US5720031  (LINDSAY BRENT [US]);
 [Y]  - MCLEOD G R, "BUILT-IN SYSTEM TEST AND FAULT LOCATION", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE. WASHINGTON, OCT. 2 - 6, 1994., NEW YORK, IEEE., US, US, (19941001), ISBN 978-0-7803-2103-8, pages 291 - 299, XP002927255
 [X]  - BURWICK W, DAUM W, "HIGH YIELD MULTICHIP MODULES BASED ON MINIMAL IC PRETEST", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE. WASHINGTON, OCT. 2 - 6, 1994., NEW YORK, IEEE., US, US, (19941001), ISBN 978-0-7803-2103-8, pages 30 - 40, XP002927256
 [Y]  - YUE J, ET AL., "AN EFFECTIVE METHOD TO SCREEN SOI WAFERS FOR MASS PRODUCTION", INTERNATIONAL SOI CONFERENCE PROCEEDINGS. NANTUCKET ISLAND, OCT. 3 - 6, 1994., NEW YORK, IEEE., US, US, (19941001), doi:10.1109/SOI.1994.514272, ISBN 978-0-7803-2407-7, page 113/114, XP002927257

DOI:   http://dx.doi.org/10.1109/SOI.1994.514272
 [Y]  - MULLENIX P. ET AL., "Limited Yield Estimation fo Visual Defect Sources", IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING,, (199702), vol. 10, no. 1, pages 17 - 23, XP002927258

DOI:   http://dx.doi.org/10.1109/66.554478
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.