| Angeführt in | Internationale Recherche | Art: | Nichtpatentliteratur | Angaben zur Veröffentlichung: | [PX] LIAU E ET AL: "Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits", CONFERENCE PROCEEDINGS ARTICLE, 25 May 2003 (2003-05-25), pages 105 - 110, XP010658168 [PX] 1,15 * column 8 - column 11; figure 7 * | Art: | Nichtpatentliteratur | Angaben zur Veröffentlichung: | [DA] SHIYOU ZHAO ET AL: "Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits", VLSI DESIGN, 2000. THIRTEENTH INTERNATIONAL CONFERENCE ON CALCUTTA, INDIA 3-7 JAN. 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 3 January 2000 (2000-01-03), pages 168 - 173, XP010365932, ISBN: 0-7695-0487-6 [DA] 1,15 * the whole document * | DOI: | http://dx.doi.org/10.1109/ICVD.2000.812604 |
