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EP1139419
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EP About this file: EP1139419
| EP1139419 - Method of manufacturing an electrically programmable, non-volatile memory with logic circuitry [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 20.02.2009 Database last updated on 13.07.2024 | Most recent event Tooltip | 20.02.2009 | Application deemed to be withdrawn | published on 25.03.2009 [2009/13] | Applicant(s) | For all designated states STMicroelectronics Srl Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | [N/P] |
| Former [2001/40] | For all designated states STMicroelectronics S.r.l. Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | Inventor(s) | 01 /
Peschiaroli, Daniela Via Porpora, 154 20131 Milano / IT | 02 /
Maurelli, Alfonso Via Moro, 6 20050 Sulbiate (Milano) / IT | 03 /
Palumbo, Elisabetta Via Carlo Vittadini, 6 20136 Milano / IT | 04 /
Piazza, Fausto Via Battisti, 12 20041 Agrate Brianza / IT | [2001/40] | Representative(s) | Maccalli, Marco, et al Jacobacci & Perani S.p.A. Via Senato, 8 20121 Milano / IT | [N/P] |
| Former [2001/40] | Maccalli, Marco, et al Jacobacci & Perani S.p.A. Via Senato, 8 20121 Milano / IT | Application number, filing date | 00830236.6 | 29.03.2000 | [2001/40] | Filing language | IT | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1139419 | Date: | 04.10.2001 | Language: | EN | [2001/40] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.09.2000 | Classification | IPC: | H01L21/8247, H01L27/115 | [2001/40] | CPC: |
H10B41/40 (EP,US);
H10B41/47 (EP,US);
H10B99/00 (US)
| Designated contracting states | DE, FR, GB, IT [2002/26] |
| Former [2001/40] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Herstellungsverfahren eines elektrisch programmierbaren Festwertspeichers mit Logikschaltung | [2001/40] | English: | Method of manufacturing an electrically programmable, non-volatile memory with logic circuitry | [2001/40] | French: | Procédé de fabrication d'une mémoire non-volatile programmable électriquement avec circuit logique | [2001/40] | Examination procedure | 18.03.2002 | Examination requested [2002/22] | 07.04.2002 | Loss of particular rights, legal effect: designated state(s) | 08.10.2002 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, CY, DK, ES, FI, GR, IE, LU, MC, NL, PT, SE | 02.02.2007 | Despatch of a communication from the examining division (Time limit: M06) | 07.08.2007 | Reply to a communication from the examining division | 01.10.2008 | Application deemed to be withdrawn, date of legal effect [2009/13] | 04.11.2008 | Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time [2009/13] | Fees paid | Renewal fee | 25.03.2002 | Renewal fee patent year 03 | 28.03.2003 | Renewal fee patent year 04 | 29.03.2004 | Renewal fee patent year 05 | 25.03.2005 | Renewal fee patent year 06 | 29.03.2006 | Renewal fee patent year 07 | 27.03.2007 | Renewal fee patent year 08 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 23.07.2002 | AT M01 Not yet paid | 23.07.2002 | BE M01 Not yet paid | 23.07.2002 | CH M01 Not yet paid | 23.07.2002 | CY M01 Not yet paid | 23.07.2002 | DK M01 Not yet paid | 23.07.2002 | ES M01 Not yet paid | 23.07.2002 | FI M01 Not yet paid | 23.07.2002 | GR M01 Not yet paid | 23.07.2002 | IE M01 Not yet paid | 23.07.2002 | LU M01 Not yet paid | 23.07.2002 | MC M01 Not yet paid | 23.07.2002 | NL M01 Not yet paid | 23.07.2002 | PT M01 Not yet paid | 23.07.2002 | SE M01 Not yet paid | Additional fee for renewal fee | 31.03.2008 | 09 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US5668034 (SERY GEORGE E [US], et al) [Y] 1-8 * the whole document *; | [A]US5768194 (MATSUBARA KIYOSHI [JP], et al) [A] 1-8 * column 43, line 44 - column 47, line 61; figures 58A-62 *; | [A]US5908311 (CHI MIN-HWA [US], et al) [A] 1-8* the whole document *; | [Y] - TAKEUCHI Y ET AL, "A SELF-ALIGNED STI PROCESS INTEGRATION FOR LOW COST AND HIGHLY RELIABLE 1GBIT FLASH MEMORIES", SYMPOSIUM ON VLSI TECHNOLOGY,US,NEW YORK, NY: IEEE, (19980609), vol. CONF. 18, ISBN 0-7803-4771-4, pages 102 - 103, XP000802764 [Y] 1-8 * the whole document * | Examination | EP1109217 |