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Extract from the Register of European Patents

EP About this file: EP1161767

EP1161767 - Method of making a vertical MOS transistor device [Right-click to bookmark this link]
Former [2001/50]METHOD FOR PRODUCING A BODY AREA FOR A VERTICAL MOS TRANSISTOR ARRAY WITH REDUCED SPECIFIC STARTING RESISTOR
[2010/47]
StatusNo opposition filed within time limit
Status updated on  23.03.2012
Database last updated on 25.09.2024
Most recent event   Tooltip04.05.2012Lapse of the patent in a contracting state
New state(s): IT		published on 06.06.2012  [2012/23]
Applicant(s)For all designated states
Infineon Technologies AG
Am Campeon 1-12
85579 Neubiberg / DE
[2010/22]
Former [2001/50]For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81669 München / DE
Inventor(s)01 / HIRLER, Franz
Mozartstrasse 4
D-84424 Isen / DE
02 / KANERT, Werner
Otto-Mair-Ring 31
D-83607 Holzkirchen / DE
03 / GASSEL, Helmut
37007 Ashover Court
Farmington Hills, MI 48335 / US
04 / STRACK, Helmut
Speyerer Strasse 6
D-80804 München / DE
05 / PAIRITSCH, Herbert
Neckheimgasse 24
A-9020 Klagenfurt / AT
 [2001/50]
Representative(s)Bickel, Michael
Westphal, Mussgnug & Partner
Patentanwälte
Herzog-Wilhelm-Strasse 26
80331 München / DE
[N/P]
Former [2007/49]Bickel, Michael
Herzog-Wilhelm-Str. 26
80331 München / DE
Former [2001/50]Bickel, Michael
Westphal - Mussgnug & Partner Patentanwälte Mozartstrasse 8
80336 München / DE
Application number, filing date00918684.203.03.2000
[2001/50]
WO2000DE00677
Priority number, dateDE1999100956304.03.1999         Original published format: DE 19909563
[2001/50]
Filing languageDE
Procedural languageDE
PublicationType: A2 Application without search report
No.:WO0052750
Date:08.09.2000
Language:DE
[2000/36]
Type: A2 Application without search report 
No.:EP1161767
Date:12.12.2001
Language:DE
The application published by WIPO in one of the EPO official languages on 08.09.2000 takes the place of the publication of the European patent application.
[2001/50]
Type: B1 Patent specification 
No.:EP1161767
Date:18.05.2011
Language:DE
[2011/20]
Search report(s)International search report - published on:EP09.08.2001
ClassificationIPC:H01L21/336, H01L21/331, H01L21/265, H01L21/225, H01L29/78, H01L29/739, H01L29/10
[2010/47]
CPC:
H01L29/7802 (EP,US); H01L29/0634 (EP,US); H01L29/1095 (EP,US);
H01L29/66734 (EP,US); H01L29/7813 (EP,US); H01L29/66333 (EP,US);
H01L29/66348 (EP,US); H01L29/66712 (EP,US); H01L29/7397 (EP,US) (-)
Former IPC [2001/50]H01L21/336, H01L21/331, H01L29/10, H01L29/78, H01L29/739, H01L21/225
Designated contracting statesAT,   DE,   FR,   GB,   IE,   IT [2004/22]
Former [2001/50]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Verfahren zur Herstellung einer vertikalen MOS-Transistoranordnung[2010/47]
English:Method of making a vertical MOS transistor device[2010/47]
French:Méthode de fabrication d'un dispositif à transistor MOS vertical[2010/47]
Former [2001/50]VERFAHREN ZUR HERSTELLUNG EINES BODYGEBIETES FÜR EINE VERTIKALE MOS-TRANSISTORANORDNUNG MIT VERRINGERTEM SPEZIFISCHEM EINSCHALTWIDERSTAND
Former [2001/50]METHOD FOR PRODUCING A BODY AREA FOR A VERTICAL MOS TRANSISTOR ARRAY WITH REDUCED SPECIFIC STARTING RESISTOR
Former [2001/50]PROCEDE DE PRODUCTION D'UNE ZONE DE CORPS POUR UN ENSEMBLE TRANSISTOR MOS VERTICAL PRESENTANT UNE RESISTANCE AU DECLENCHEMENT SPECIFIQUE REDUITE
Entry into regional phase23.08.2001National basic fee paid 
23.08.2001Designation fee(s) paid 
23.08.2001Examination fee paid 
Examination procedure18.09.2000Request for preliminary examination filed
International Preliminary Examining Authority: EP
23.08.2001Examination requested  [2001/50]
22.05.2006Despatch of a communication from the examining division (Time limit: M06)
01.12.2006Reply to a communication from the examining division
23.07.2009Despatch of a communication from the examining division (Time limit: M06)
02.02.2010Reply to a communication from the examining division
14.01.2011Communication of intention to grant the patent
05.04.2011Fee for grant paid
05.04.2011Fee for publishing/printing paid
Divisional application(s)EP10009591.8  / EP2261961
Opposition(s)21.02.2012No opposition filed within time limit [2012/17]
Fees paidRenewal fee
23.03.2002Renewal fee patent year 03
26.03.2003Renewal fee patent year 04
17.03.2004Renewal fee patent year 05
19.03.2005Renewal fee patent year 06
29.03.2006Renewal fee patent year 07
27.03.2007Renewal fee patent year 08
18.03.2008Renewal fee patent year 09
17.03.2009Renewal fee patent year 10
16.03.2010Renewal fee patent year 11
08.03.2011Renewal fee patent year 12
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipIE18.05.2011
IT18.05.2011
[2012/23]
Former [2012/08]IE18.05.2011
Cited inInternational search[XA]JPS6448464  ;
 [Y]JPH09213939  ;
 [Y]JPS57188877  ;
 [DY]US4837606  (GOODMAN LAWRENCE A [US], et al) [DY] 1-8 * column 3, line 34 - column 5, line 63; figures 2,3 * * column 6, line 9 - line 47 *;
 [E]EP1009036  (ST MICROELECTRONICS SRL [IT]) [E] 1,2,5-7 * column 2, line 29 - column 5, line 4; figures 1-6 ** column 6, line 24 - line 32 *;
 [XA]  - PATENT ABSTRACTS OF JAPAN, (19890609), vol. 013, no. 248, Database accession no. (E - 770), & JP01048464 A 19890222 (HITACHI LTD) [X] 1,2 * abstract * * Spalten 6,7;Abbildungen 1,3-5 * [A] 4-6
 [Y]  - PATENT ABSTRACTS OF JAPAN, (19971225), vol. 1997, no. 12, & JP09213939 A 19970815 (NEC CORP) [Y] 1-8 * abstract * * Absätze 0022,0025,0040,0041; Abbildungen 1,2,4,5 *
 [Y]  - PATENT ABSTRACTS OF JAPAN, (19830215), vol. 007, no. 036, Database accession no. (E - 158), & JP57188877 A 19821119 (NIPPON DENKI KK) [Y] 3-8 * abstract *
 [A]  - DEBOY G ET AL, "NEW GENERATION OF HIGH VOLTAGE MOSFETS BREAKS THE LIMIT LINE OF SILICON", INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, SAN FRANCISCO, CA, USA, IEEE, NEW YORK, NY, USA, (19981206), ISBN 0-7803-4775-7, pages 683 - 685, XP000859463 [A] 1,4 * abstract * * Absatz "Technology"; Abbildung 2 *
by applicantJPS57188877
 JPS6448464
 JPH09213939
    - DEBOY ET AL., "International Electron Devices Meeting", TECHNICAL DIGEST, (19981206), pages 683 - 685
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.