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Extract from the Register of European Patents

EP About this file: EP1116130

EP1116130 - NETWORK OF PARALLEL PROCESSORS FAULT-TOLERANT TOWARDS SAID PROCESSORS AND RECONFIGURATION METHOD APPLICABLE TO SUCH A NETWORK [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  05.05.2006
Database last updated on 16.11.2024
Most recent event   Tooltip25.05.2007Change - lapse in a contracting state
Updated state(s): LU		published on 27.06.2007  [2007/26]
Applicant(s)For all designated states
COMMISSARIAT A L'ENERGIE ATOMIQUE
31-33, rue de la Fédération
75752 Paris Cédex 15 / FR
[2005/25]
Former [2001/29]For all designated states
COMMISSARIAT A L'ENERGIE ATOMIQUE
31-33, rue de la Fédération
75752 Paris Cédex 15 / FR
Inventor(s)01 / CLERMIDY, Fabien
101b, rue du 8 Mai 1945
F-91300 Massy / FR
02 / COLLETTE, Thierry
Résidence Les Pampres, Bâtiment A
F-91940 Les Ulis / FR
 [2001/29]
Representative(s)Weber, Etienne Nicolas, et al
BREVALEX
95 rue d'Amsterdam
75378 Paris Cedex 8 / FR
[N/P]
Former [2001/29]Weber, Etienne Nicolas, et al
c/o Brevatome, 3, rue du Docteur Lancereaux
75008 Paris / FR
Application number, filing date00949598.730.06.2000
[2001/29]
WO2000FR01860
Priority number, dateFR1999000855302.07.1999         Original published format: FR 9908553
[2001/29]
Filing languageFR
Procedural languageFR
PublicationType: A1 Application with search report
No.:WO0102975
Date:11.01.2001
Language:FR
[2001/02]
Type: A1 Application with search report 
No.:EP1116130
Date:18.07.2001
Language:FR
The application published by WIPO in one of the EPO official languages on 11.01.2001 takes the place of the publication of the European patent application.
[2001/29]
Type: B1 Patent specification 
No.:EP1116130
Date:22.06.2005
Language:FR
[2005/25]
Search report(s)International search report - published on:EP11.01.2001
ClassificationIPC:G06F15/80, G06F11/20
[2001/29]
CPC:
G06F11/2051 (EP,US); G06F11/2025 (EP,US); G06F15/8023 (EP,US);
G06F11/2041 (EP,US)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE [2001/29]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
SINot yet paid
TitleGerman:GATTER VON PARALLELEN PROZESSOREN MIT FEHLERTOLERANZ DER PROZESSOREN UND REKONFIGURIERUNGSVERFAHREN DAFÜR[2001/29]
English:NETWORK OF PARALLEL PROCESSORS FAULT-TOLERANT TOWARDS SAID PROCESSORS AND RECONFIGURATION METHOD APPLICABLE TO SUCH A NETWORK[2001/29]
French:RESEAU DE PROCESSEURS PARALLELES AVEC TOLERANCE AUX FAUTES DE CES PROCESSEURS, ET PROCEDE DE RECONFIGURATION APPLICABLE A UN TEL RESEAU[2001/29]
Entry into regional phase15.02.2001National basic fee paid 
15.02.2001Designation fee(s) paid 
15.02.2001Examination fee paid 
Examination procedure16.02.2001Examination requested  [2001/29]
07.01.2005Communication of intention to grant the patent
11.04.2005Fee for grant paid
11.04.2005Fee for publishing/printing paid
Opposition(s)23.03.2006No opposition filed within time limit [2006/23]
Fees paidRenewal fee
24.06.2002Renewal fee patent year 03
23.06.2003Renewal fee patent year 04
21.06.2004Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
CH30.06.2005
CY30.06.2005
LI30.06.2005
LU30.06.2005
MC30.06.2005
DK22.09.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
[2007/26]
Former [2007/20]AT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
CH30.06.2005
CY30.06.2005
LI30.06.2005
MC30.06.2005
LU22.08.2005
DK22.09.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2007/08]AT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
CH30.06.2005
LI30.06.2005
MC30.06.2005
LU22.08.2005
DK22.09.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2006/33]AT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
CH30.06.2005
LI30.06.2005
MC30.06.2005
DK22.09.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2006/28]AT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
MC30.06.2005
DK22.09.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2006/26]AT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
DK22.09.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2006/25]AT22.06.2005
FI22.06.2005
IE22.06.2005
BE30.06.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2006/14]AT22.06.2005
FI22.06.2005
GR22.09.2005
SE22.09.2005
ES03.10.2005
PT29.11.2005
Former [2006/13]AT22.06.2005
FI22.06.2005
SE22.09.2005
Former [2005/52]FI22.06.2005
SE22.09.2005
Former [2005/50]SE22.09.2005
Cited inInternational search[DA]  - MAHAPATRA N R ET AL, "HARDWARE-EFFICIENT AND HIGHLY-RECONFIGURABLE 4- AND 2-TRACK FAULT-TOLERANT DESIGNS FOR MESH-CONNECTED MULTICOMPUTERS", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING,US,LOS ALAMITOS, IEEE COMP. SOC. PRESS, (1996), vol. CONF. 26, ISBN 0-8186-7261-7, pages 272 - 281, XP000679291 [DA] 1-8 * page 272, column R, line 4 - page 273, column R, line 25; figure 1 *

DOI:   http://dx.doi.org/10.1109/FTCS.1996.535880
 [A]  - POPLI S P ET AL, "A RECONFIGURABLE VLSI ARRAY FOR RELIABILITY AND YIELD ENHANCEMENT", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SYSTOLIC ARRAYS. FROM 1990 PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON APPLICATION SPECIFIC ARRAY PROCESSORS,US,WASHINGTON, IEEE COMP. SOC. PRESS, (1988), vol. CONF. 2, pages 631 - 642, XP000756117 [A] 1-3,6-8 * page 633, paragraph 4 - page 638 *
 [A]  - JOHN L K ET AL, "A DYNAMICALLY RECONFIGURABLE INTERCONNECT FOR ARRAY PROCESSORS", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,US,IEEE INC. NEW YORK, (19980301), vol. 6, no. 1, ISSN 1063-8210, pages 150 - 157, XP000739209 [A] 1-3,6,7 * page 151, paragraphs II,III - page 156 *

DOI:   http://dx.doi.org/10.1109/92.661257
 [A]  - SHIGEI N ET AL, "ON EFFICIENT SPARE ARRANGEMENTS AND AN ALGORITHM WITH RELOCATING SPARES FOR RECONFIGURING PROCESSOR ARRAYS", IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, COMMUNICATIONS AND COMPUTER SCIENCES,JP,INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, (19970601), vol. E80-A, no. 6, ISSN 0916-8508, pages 988 - 995, XP000740592 [A] 1 * page 988, paragraph 2 - page 990; figure 1 *
 [PX]  - CLERMIDY F ET AL, "A new placement algorithm dedicated to parallel computers: bases and application", PROCEEDINGS 1999 PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS 1999 PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, HONG KONG, 16-17 DEC. 1999, 1999, Los Alamitos, CA, USA, IEEE Comput. Soc, USA, ISBN 0-7695-0371-3, pages 242 - 249, XP002139232 [PX] 1-11 * the whole document *

DOI:   http://dx.doi.org/10.1109/PRDC.1999.816235
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.