blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Extract from the Register of European Patents

EP About this file: EP1271317

EP1271317 - System-on-chip with time redundancy operation [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  27.02.2004
Database last updated on 31.08.2024
Most recent event   Tooltip27.02.2004Application deemed to be withdrawnpublished on 14.04.2004  [2004/16]
Applicant(s)For all designated states
Nagracard S.A.
22, route de Genève
1033 Cheseaux-sur-Lausanne / CH
[2003/01]
Inventor(s)01 / Osen, Karl
Rue du Mandement 453
1282 Dardagny / CH
 [2003/01]
Representative(s)Wenger, Joel-Théophile
Leman Consulting S.A.
Chemin de Précossy 31
1260 Nyon / CH
[N/P]
Former [2003/01]Wenger, Joel-Théophile
Leman Consulting S.A. 62 route de Clementy
1260 Nyon / CH
Application number, filing date01115915.929.06.2001
[2003/01]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1271317
Date:02.01.2003
Language:EN
[2003/01]
Search report(s)(Supplementary) European search report - dispatched on:EP29.05.2002
ClassificationIPC:G06F11/14
[2003/01]
CPC:
G06F11/1497 (EP)
Designated contracting states(deleted) [2003/39]
Former [2003/01]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:System-auf-Chip mit Zeitredundanzoperation[2003/01]
English:System-on-chip with time redundancy operation[2003/01]
French:Système-sur-puce avec exécution de redondance de temps[2003/01]
Examination procedure03.07.2003Application deemed to be withdrawn, date of legal effect  [2004/16]
06.11.2003Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time  [2004/16]
Fees paidRenewal fee
23.12.2002Renewal fee patent year 03
Penalty fee
Penalty fee Rule 85a EPC 1973
11.08.2003AT   M01   Not yet paid
11.08.2003BE   M01   Not yet paid
11.08.2003CH   M01   Not yet paid
11.08.2003CY   M01   Not yet paid
11.08.2003DE   M01   Not yet paid
11.08.2003DK   M01   Not yet paid
11.08.2003ES   M01   Not yet paid
11.08.2003FI   M01   Not yet paid
11.08.2003FR   M01   Not yet paid
11.08.2003GB   M01   Not yet paid
11.08.2003GR   M01   Not yet paid
11.08.2003IE   M01   Not yet paid
11.08.2003IT   M01   Not yet paid
11.08.2003LU   M01   Not yet paid
11.08.2003MC   M01   Not yet paid
11.08.2003NL   M01   Not yet paid
11.08.2003PT   M01   Not yet paid
11.08.2003SE   M01   Not yet paid
11.08.2003TR   M01   Not yet paid
Penalty fee Rule 85b EPC 1973
11.08.2003M01   Not yet paid
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]US6247151  (POISNER DAVID I [US]);
 [A]GB2293469  (SECR DEFENCE [GB]);
 [XA]  - NICOLAIDIS M ET AL, "Concurrent Checking for VLSI", MICROELECTRONIC ENGINEERING, ELSEVIER PUBLISHERS BV., AMSTERDAM, NL, (199911), vol. 49, no. 1-2, ISSN 0167-9317, pages 139 - 156, XP004182058 [X] 1 * page 151, column R, line 18 - page 152, column R, line 34 * [A] 2

DOI:   http://dx.doi.org/10.1016/S0167-9317(99)00435-9
 [X]  - R. KARRI ET AL., "Concurrent Error Detection of Fault-Based Side-channel Cryptanalysis of 128-Bit Symmetric Block Ciphers", PROCEEDINGS OF THE 38TH DESIGN AUTOMATION CONFERENCE, Las Vegas, USA, (20010618), pages 579 - 584, XP002190412 [X] 1 * the whole document *

DOI:   http://dx.doi.org/10.1145/378239.379027
 [A]  - THOU-HO CHEN ET AL, "CONCURRENT ERROR-DETECTABLE BUTTERFLY CHIP FOR REAL-TIME FFT PROCESSING THROUGH TIME REDUNDANCY", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, (19930501), vol. 28, no. 5, ISSN 0018-9200, pages 537 - 547, XP000368741 [A] 1 * the whole document *

DOI:   http://dx.doi.org/10.1109/4.229402
 [A]  - ROTENBERG E, "AR-SMT: A MICROARCHITECTURAL APPROACH TO FAULT TOLERANCE IN MICROPROCESSORS", 29TH ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING. DIGEST OF PAPERS. (FTCS-29). MADISON, WI, JUNE 15 - 18, 1999, ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, LOS ALMITOS, CA: IEEE COMP. SOC, US, (19990615), ISBN 0-7803-5763-9, pages 84 - 91, XP000873029 [A] 1 * the whole document *
 [A]  - D.K. PRADHAN, Fault-Tolerant Computer System Design, NEW JERSEY, USA, PRENTICE HALL PTR, (1995), 226280, XP002190413 [A] * page 43, line 16 - page 47, line 24 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.