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Extract from the Register of European Patents

EP About this file: EP1189489

EP1189489 - Control circuit with configuration intput [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  06.04.2007
Database last updated on 25.09.2024
Most recent event   Tooltip12.12.2008Lapse of the patent in a contracting state
New state(s): CY
published on 14.01.2009  [2009/03]
Applicant(s)For all designated states
TridonicAtco GmbH & Co. KG
Färbergasse 15
6851 Dornbirn / AT
[2002/18]
Former [2002/12]For all designated states
Tridonic Bauelemente GmbH
Färbergasse 15
6851 Dornbirn / AT
Inventor(s)01 / Zudrell-Koch, Stefan
Rohrmoos 60
6850 Dornbirn / AT
02 / Knödgen, Horst
Hitlstrasse 64
80997 München / DE
 [2002/12]
Representative(s)Rupp, Christian, et al
Mitscherlich PartmbB
Patent- und Rechtsanwälte
Postfach 33 06 09
80066 München / DE
[N/P]
Former [2004/32]Rupp, Christian, Dipl.-Phys., et al
Mitscherlich & Partner, Patent- und Rechtsanwälte, Postfach 33 06 09
80066 München / DE
Former [2002/12]Schmidt-Evers, Jürgen, Dipl.-Ing., et al
Patentanwälte Mitscherlich & Partner, Sonnenstrasse 33
80331 München / DE
Application number, filing date01122010.013.09.2001
[2002/12]
Priority number, dateDE200014571315.09.2000         Original published format: DE 10045713
DE200112858713.06.2001         Original published format: DE 10128587
[2002/12]
Filing languageDE
Procedural languageDE
PublicationType: A1 Application with search report 
No.:EP1189489
Date:20.03.2002
Language:DE
[2002/12]
Type: B1 Patent specification 
No.:EP1189489
Date:31.05.2006
Language:DE
[2006/22]
Search report(s)(Supplementary) European search report - dispatched on:EP23.01.2002
ClassificationIPC:H05B41/36, H05B41/38
[2002/12]
CPC:
H05B41/38 (EP); H05B41/282 (EP); H05B41/36 (EP);
Y02B20/00 (EP)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2002/12]
TitleGerman:Steuerschaltung mit Konfigurierungseingang[2002/12]
English:Control circuit with configuration intput[2002/12]
French:Circuit de commande avec une entrée de configuration[2002/12]
Examination procedure02.07.2002Examination requested  [2002/36]
31.07.2003Despatch of a communication from the examining division (Time limit: M03)
22.10.2003Reply to a communication from the examining division
07.12.2004Despatch of a communication from the examining division (Time limit: M02)
03.02.2005Reply to a communication from the examining division
24.05.2005Despatch of a communication from the examining division (Time limit: M04)
23.09.2005Reply to a communication from the examining division
13.12.2005Communication of intention to grant the patent
15.03.2006Fee for grant paid
15.03.2006Fee for publishing/printing paid
Opposition(s)01.03.2007No opposition filed within time limit [2007/19]
Fees paidRenewal fee
29.09.2003Renewal fee patent year 03
29.09.2004Renewal fee patent year 04
29.09.2005Renewal fee patent year 05
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See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipCY31.05.2006
FI31.05.2006
IE31.05.2006
TR31.05.2006
DK31.08.2006
SE31.08.2006
GR01.09.2006
ES11.09.2006
LU13.09.2006
BE30.09.2006
MC30.09.2006
PT31.10.2006
[2009/03]
Former [2008/37]FI31.05.2006
IE31.05.2006
TR31.05.2006
DK31.08.2006
SE31.08.2006
GR01.09.2006
ES11.09.2006
LU13.09.2006
BE30.09.2006
MC30.09.2006
PT31.10.2006
Former [2008/19]FI31.05.2006
IE31.05.2006
DK31.08.2006
SE31.08.2006
GR01.09.2006
ES11.09.2006
BE30.09.2006
MC30.09.2006
PT31.10.2006
Former [2007/45]FI31.05.2006
IE31.05.2006
DK31.08.2006
SE31.08.2006
ES11.09.2006
BE30.09.2006
MC30.09.2006
PT31.10.2006
Former [2007/37]FI31.05.2006
IE31.05.2006
IT31.05.2006
DK31.08.2006
SE31.08.2006
ES11.09.2006
BE30.09.2006
MC30.09.2006
PT31.10.2006
Former [2007/36]FI31.05.2006
IE31.05.2006
IT31.05.2006
DK31.08.2006
SE31.08.2006
ES11.09.2006
BE30.09.2006
PT31.10.2006
Former [2007/31]FI31.05.2006
IE31.05.2006
DK31.08.2006
SE31.08.2006
ES11.09.2006
BE30.09.2006
PT31.10.2006
Former [2007/12]FI31.05.2006
IE31.05.2006
DK31.08.2006
SE31.08.2006
ES11.09.2006
PT31.10.2006
Former [2007/09]FI31.05.2006
DK31.08.2006
SE31.08.2006
ES11.09.2006
Former [2006/51]FI31.05.2006
SE31.08.2006
ES11.09.2006
Former [2006/50]SE31.08.2006
ES11.09.2006
Former [2006/48]SE31.08.2006
Documents cited:Search[A]US5187414  (FELLOWS MARK W [US], et al) [A] 5-13 * abstract * * column 4 * * column 6, line 1 - column 9, line 8 *;
 [A]WO9818296  (LOGICAL TECHNOLOGY LIMITED, et al) [A] 1-13 * abstract * * page 1, line 19 - page 3, line 10 *;
 [A]WO9839949  (TRIDONIC BAUELEMENTE [AT], et al) [A] 1-13 * the whole document *;
 [A]WO0024230  (MITSUBISHI ELECTRIC CORP [JP], et al) [A] 1-13;
 [PA]EP1041862  (MITSUBISHI ELECTRIC CORP [JP], et al) [PA] 1-13 * abstract ** paragraphs [0025] , [0029] , [0064] , [0065] , [0078] *;
 [A]  - UNITRODE, linear integrated circuits data and applications handbook, USA, UNITRODE INTEGRATED CIRCUITS CORP, (1990), XP002172830 [A] 2-4 * pages 5-64 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.