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EP1128548
European procedure
Extract from the Register of European Patents
EP About this file: EP1128548
| EP1128548 - FET bias circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.08.2008 Database last updated on 20.09.2024 | Most recent event Tooltip | 08.08.2008 | No opposition filed within time limit | published on 10.09.2008 [2008/37] | Applicant(s) | For all designated states JAPAN RADIO CO., LTD 1-1, Shimorenjaku 5-chome Mitaka-shi Tokyo 181-8510 / JP | [2007/40] |
| Former [2001/35] | For all designated states JAPAN RADIO CO., LTD 1-1, Shimorenjaku 5-chome Mitaka-shi, Tokyo 181-8510 / JP | Inventor(s) | 01 /
Sakamoto Hironori, c/o Japan Radio Co. Ltd. 1-1, Shimorenjaku 5-chome Mitaka-shi, Tokyo 181-8510 / JP | 02 /
Honda, Tamaki, c/o Japan Radio Co. Ltd. 1-1, Shimorenjaku 5-chome Mitaka-shi, Tokyo 181-8510 / JP | 03 /
Takahashi, Taketo, c/o Japan Radio Co. Ltd. 1-1, Shimorenjaku 5-chome Mitaka-shi, Tokyo 181-8510 / JP | [2001/35] | Representative(s) | McLeish, Nicholas Alistair Maxwell, et al Boult Wade Tennant Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB | [N/P] |
| Former [2001/35] | McLeish, Nicholas Alistair Maxwell, et al Boult Wade Tennant Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB | Application number, filing date | 01300842.0 | 31.01.2001 | [2001/35] | Priority number, date | JP20000045312 | 23.02.2000 Original published format: JP 2000045312 | [2001/35] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1128548 | Date: | 29.08.2001 | Language: | EN | [2001/35] | Type: | A3 Search report | No.: | EP1128548 | Date: | 15.01.2003 | [2003/03] | Type: | B1 Patent specification | No.: | EP1128548 | Date: | 03.10.2007 | Language: | EN | [2007/40] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.11.2002 | Classification | IPC: | H03F1/30 | [2001/35] | CPC: |
H03F1/306 (EP,US);
H03F1/30 (KR);
H03F2200/447 (EP,US);
H03F2200/75 (EP,US)
| Designated contracting states | DE, FI, FR, GB, SE [2003/40] |
| Former [2001/35] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR | Title | German: | Vorspannungsschaltung für einen Feldeffekttransistor | [2001/35] | English: | FET bias circuit | [2001/35] | French: | Circuit de polarisation pour un transistor à effet de champ | [2001/35] | Examination procedure | 03.03.2003 | Examination requested [2003/18] | 16.03.2006 | Despatch of a communication from the examining division (Time limit: M04) | 22.05.2006 | Reply to a communication from the examining division | 16.04.2007 | Communication of intention to grant the patent | 16.08.2007 | Fee for grant paid | 16.08.2007 | Fee for publishing/printing paid | Opposition(s) | 04.07.2008 | No opposition filed within time limit [2008/37] | Fees paid | Renewal fee | 23.12.2002 | Renewal fee patent year 03 | 24.11.2003 | Renewal fee patent year 04 | 26.01.2005 | Renewal fee patent year 05 | 18.01.2006 | Renewal fee patent year 06 | 18.01.2007 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US5808515 (TSURUOKA YOSHIYASU [JP], et al) [X] 1 * column 4, line 51 - column 6, line 17; figure 1 *; | [A]EP0942524 (NOKIA MOBILE PHONES LTD [FI]) [A] 2,3 * column A; figure 3 * * column 3, paragraph 11 *; | [A] - GALLUZZI P, "VOLTAGE LIMITER IS 523 TEMPERATUR STABLE", ELECTRONIC DESIGN, PENTON PUBLISHING, CLEVELAND, OH, US, (19891012), vol. 37, no. 21, ISSN 0013-4872, page 86, XP000076210 [A] 2 * column W * |