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EP1124262
European procedure
Extract from the Register of European Patents
EP About this file: EP1124262
| EP1124262 - Integrated circuit comprising a multilayer dielectric stack and method [Right-click to bookmark this link] | |||
| Former [2001/33] | Multilayer dielectric stack and method | ||
| [2005/36] | Status | No opposition filed within time limit Status updated on 23.02.2007 Database last updated on 02.11.2024 | Most recent event Tooltip | 23.02.2007 | No opposition filed within time limit | published on 28.03.2007 [2007/13] | Applicant(s) | For all designated states Sharp Kabushiki Kaisha 22-22, Nagaike-cho Abeno-ku Osaka-shi, Osaka 545-8522 / JP | [N/P] |
| Former [2006/16] | For all designated states SHARP KABUSHIKI KAISHA 22-22, Nagaike-cho Abeno-ku Osaka-shi, Osaka 545-8522 / JP | ||
| Former [2001/33] | For all designated states Sharp Kabushiki Kaisha 22-22, Nagaike-cho, Abeno-ku Osaka-shi, Osaka 545-8522 / JP | Inventor(s) | 01 /
Ma, Yanjun 18311 SE 24th Way Vancouver, WA 98683 / US | 02 /
Ono, Yoshi 2526 NW 24th Circle Camas, WA 98607 / US | [2001/33] | Representative(s) | Brown, Kenneth Richard, et al R.G.C. Jenkins & Co 26 Caxton Street London SW1H 0RJ / GB | [N/P] |
| Former [2001/33] | Brown, Kenneth Richard, et al R.G.C. Jenkins & Co. 26 Caxton Street London SW1H 0RJ / GB | Application number, filing date | 01301136.6 | 08.02.2001 | [2001/33] | Priority number, date | US20000502420 | 11.02.2000 Original published format: US 502420 | [2001/33] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1124262 | Date: | 16.08.2001 | Language: | EN | [2001/33] | Type: | A3 Search report | No.: | EP1124262 | Date: | 09.10.2002 | [2002/41] | Type: | B1 Patent specification | No.: | EP1124262 | Date: | 19.04.2006 | Language: | EN | [2006/16] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 26.08.2002 | Classification | IPC: | H01L29/51, H01L21/28, H01L21/336 | [2002/41] | CPC: |
H01L21/28185 (EP,US);
H01L21/18 (KR);
H01L21/28194 (EP,US);
H01L29/513 (EP,US);
H01L29/66583 (EP,US);
H01L21/28202 (EP,US);
|
| Former IPC [2001/33] | H01L29/51, H01L21/28 | Designated contracting states | DE, FR, GB [2003/30] |
| Former [2003/27] | AT, BE, CH, LI | ||
| Former [2001/33] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR | Title | German: | Integrierte Schaltung mit einem dielektrischen Schichtverbund und Verfahren | [2005/36] | English: | Integrated circuit comprising a multilayer dielectric stack and method | [2005/36] | French: | Circuit integré comportant un empilement multicouche des matériaux dielectriques et méthode | [2005/36] |
| Former [2001/33] | Dielektrischer Schichtverbund und Verfahren | ||
| Former [2001/33] | Multilayer dielectric stack and method | ||
| Former [2001/33] | Empilement multicouche des matériaux dielectriques et méthode | Examination procedure | 03.01.2003 | Examination requested [2003/10] | 14.03.2003 | Despatch of a communication from the examining division (Time limit: M06) | 10.04.2003 | Loss of particular rights, legal effect: designated state(s) | 10.04.2003 | Despatch of communication of loss of particular rights: designated state(s) DK | 23.07.2003 | Reply to a communication from the examining division | 28.08.2003 | Loss of particular rights, legal effect: designated state(s) | 28.08.2003 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, CY, ES, FI, GR, IE, IT, LU, MC, NL, PT, SE, TR | 01.12.2003 | Despatch of a communication from the examining division (Time limit: M04) | 13.04.2004 | Reply to a communication from the examining division | 26.08.2004 | Despatch of a communication from the examining division (Time limit: M02) | 29.10.2004 | Reply to a communication from the examining division | 02.09.2005 | Communication of intention to grant the patent | 09.01.2006 | Fee for grant paid | 09.01.2006 | Fee for publishing/printing paid | Opposition(s) | 22.01.2007 | No opposition filed within time limit [2007/13] | Fees paid | Renewal fee | 12.02.2003 | Renewal fee patent year 03 | 12.02.2004 | Renewal fee patent year 04 | 14.02.2005 | Renewal fee patent year 05 | 14.02.2006 | Renewal fee patent year 06 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 10.06.2003 | AT M01 Not yet paid | 10.06.2003 | BE M01 Not yet paid | 10.06.2003 | CH M01 Not yet paid | 10.06.2003 | CY M01 Not yet paid | 10.06.2003 | DK M01 Not yet paid | 10.06.2003 | ES M01 Not yet paid | 10.06.2003 | FI M01 Not yet paid | 10.06.2003 | GR M01 Not yet paid | 10.06.2003 | IE M01 Not yet paid | 10.06.2003 | IT M01 Not yet paid | 10.06.2003 | LU M01 Not yet paid | 10.06.2003 | MC M01 Not yet paid | 10.06.2003 | NL M01 Not yet paid | 10.06.2003 | PT M01 Not yet paid | 10.06.2003 | SE M01 Not yet paid | 10.06.2003 | TR M01 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY]US5688724 (YOON EUISIK [US], et al); | [A]EP0962547 (IBM [US]); | [Y]US6020243 (WALLACE ROBERT M [US], et al); |