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EP1176636
European procedure
Extract from the Register of European Patents
EP About this file: EP1176636
| EP1176636 - System for manufacturing a thin-film transistor, method of manufacturing a thin-film transistor, method of evaluationg polysilicon, and apparatus for inspecting polysilicon [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.03.2012 Database last updated on 02.11.2024 | Most recent event Tooltip | 09.03.2012 | No opposition filed within time limit | published on 11.04.2012 [2012/15] | Applicant(s) | For all designated states Sony Corporation 7-35, Kitashinagawa 6-chome Shinagawa-ku Tokyo / JP | [N/P] |
| Former [2011/18] | For all designated states Sony Corporation 7-35, Kitashinagawa 6-chome Shinagawa-ku Tokyo / JP | ||
| Former [2002/05] | For all designated states SONY CORPORATION 7-35, Kitashinagawa 6-chome Shinagawa-ku Tokyo / JP | Inventor(s) | 01 /
Wada, Hiroyuki c/o Sony Corporation, 7-35 Kitashinagawa 6-chome Shinagawa-ku, Tokyo 141-0001 / JP | 02 /
Takatoku, Makoto c/o Sony Corporation, 7-35 Kitashinagawa 6-chome Shinagawa-ku, Tokyo 141-0001 / JP | [2002/05] | Representative(s) | Ayers, Martyn Lewis Stanley J A Kemp 14 South Square Gray's Inn London WC1R 5JJ / GB | [N/P] |
| Former [2008/29] | Ayers, Martyn Lewis Stanley J.A. KEMP & CO. 14 South Square Gray's Inn London WC1R 5JJ / GB | ||
| Former [2002/05] | Ayers, Martyn Lewis Stanley J.A. KEMP & CO. 14 South Square Gray's Inn London WC1R 5LX / GB | Application number, filing date | 01306383.9 | 25.07.2001 | [2002/05] | Priority number, date | JP20000227807 | 27.07.2000 Original published format: JP 2000227807 | [2002/05] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1176636 | Date: | 30.01.2002 | Language: | EN | [2002/05] | Type: | A3 Search report | No.: | EP1176636 | Date: | 18.01.2006 | [2006/03] | Type: | B1 Patent specification | No.: | EP1176636 | Date: | 04.05.2011 | Language: | EN | [2011/18] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.12.2005 | Classification | IPC: | H01L21/66, H01L21/336, G01B11/30 | [2006/03] | CPC: |
B23K26/032 (EP,US);
H01L29/786 (KR);
H01L21/02422 (EP,KR,US);
H01L21/02488 (EP,KR,US);
H01L21/02491 (EP,KR,US);
H01L21/02505 (EP,KR,US);
H01L21/02532 (EP,KR,US);
H01L21/02675 (US);
H01L21/02678 (EP,KR,US);
H01L21/02686 (EP,KR,US);
H01L21/02691 (EP,KR,US);
H01L21/268 (EP,US);
H01L22/26 (EP,US);
H01L29/66765 (EP,US);
H01L29/78678 (EP,US);
H01L2924/0002 (EP,US)
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| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
|
| Former IPC [2002/05] | H01L21/66 | Designated contracting states | DE, FR, GB [2006/38] |
| Former [2002/05] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR | Title | German: | Herstellungssystem und Methode eines Dünnschicht-Transistors, Polysilizium-Untersuchungsmethode und Apparat | [2002/05] | English: | System for manufacturing a thin-film transistor, method of manufacturing a thin-film transistor, method of evaluationg polysilicon, and apparatus for inspecting polysilicon | [2002/05] | French: | Système et methode de fabrication d'un transistor à couche mince, méthode d'valuation de polysilicium et appareil associé | [2002/05] | Examination procedure | 27.06.2006 | Examination requested [2006/32] | 05.08.2009 | Despatch of a communication from the examining division (Time limit: M06) | 15.02.2010 | Reply to a communication from the examining division | 23.11.2010 | Communication of intention to grant the patent | 14.03.2011 | Fee for grant paid | 14.03.2011 | Fee for publishing/printing paid | Opposition(s) | 07.02.2012 | No opposition filed within time limit [2012/15] | Fees paid | Renewal fee | 14.07.2003 | Renewal fee patent year 03 | 14.07.2004 | Renewal fee patent year 04 | 13.07.2005 | Renewal fee patent year 05 | 12.07.2006 | Renewal fee patent year 06 | 13.07.2007 | Renewal fee patent year 07 | 31.03.2008 | Renewal fee patent year 08 | 10.07.2009 | Renewal fee patent year 09 | 27.07.2010 | Renewal fee patent year 10 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP2000058477 ; | [A]EP0655774 (SONY CORP [JP]) [A] 1-14 * abstract *; | [A]US5850288 (HONMA ICHIROU [JP], et al) [A] 1-14* abstract *; | [A]EP0886319 (SONY CORP [JP]) [A] 1-14 * column 3, line 24 - column 4, line 55; figures 1A,1B,4,5 *; | [A]US5946562 (KUO YUE [US]) [A] 1-14 * abstract *; | [PA]US6187088 (OKUMURA HIROSHI [JP]) [PA] 1-14; | [A] - PATENT ABSTRACTS OF JAPAN, (20000914), vol. 2000, no. 05, & JP2000058477 A 20000225 (NEC CORP) [A] 1-14 * abstract * | [A] - MEI P ET AL, "GRAIN GROWTH IN LASER DEHYDROGENATED AND CRYSTALLIZED POLYCRYSTALLINE SILICON FOR THIN FILM TRANSISTORS", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, (19940901), vol. 76, no. 5, ISSN 0021-8979, pages 3194 - 3199, XP000466425 [A] 1-14 * the whole document * DOI: http://dx.doi.org/10.1063/1.357505 | by applicant | US5825498 | US5864394 | US6136632 |