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EP1184909
European procedure
Extract from the Register of European Patents
EP About this file: EP1184909
| EP1184909 - Method of manufacturing an integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 01.06.2007 Database last updated on 11.09.2024 | Most recent event Tooltip | 01.06.2007 | No opposition filed within time limit | published on 04.07.2007 [2007/27] | Applicant(s) | For all designated states Agere Systems Guardian Corporation 9333 S John Young Parkway, Room 301E1211 Orlando Florida 32819 / US | [2006/30] |
| Former [2002/10] | For all designated states Agere Systems Guardian Corporation 9333 S John Young Parkway, Room 301E1211 Orlando, Florida 32819 / US | Inventor(s) | 01 /
Krutsick, Thomas J 23 Crestview Drive Fleetwood, PA 19522 / US | [2002/10] | Representative(s) | Williams, David John, et al Page White & Farrer Limited Bedford House 21A John Street London WC1N 2BF / GB | [N/P] |
| Former [2002/10] | Williams, David John, et al Page White & Farrer, 54 Doughty Street London WC1N 2LS / GB | Application number, filing date | 01307010.7 | 17.08.2001 | [2002/10] | Priority number, date | US20000650606 | 30.08.2000 Original published format: US 650606 | [2002/10] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1184909 | Date: | 06.03.2002 | Language: | EN | [2002/10] | Type: | A3 Search report | No.: | EP1184909 | Date: | 13.10.2004 | [2004/42] | Type: | B1 Patent specification | No.: | EP1184909 | Date: | 26.07.2006 | Language: | EN | [2006/30] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.08.2004 | Classification | IPC: | H01L29/8605, H01L29/06 | [2002/10] | CPC: |
H01L29/66166 (EP,US);
H01L27/04 (KR);
H01L29/8605 (EP,US)
| Designated contracting states | DE, FR, GB [2005/27] |
| Former [2002/10] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR | Title | German: | Herstellungsverfahren für integrierten Schaltkreis | [2002/10] | English: | Method of manufacturing an integrated circuit | [2002/10] | French: | Procédé de fabrication d'un circuit integré | [2002/10] | Examination procedure | 07.01.2005 | Examination requested [2005/10] | 13.04.2005 | Despatch of a communication from the examining division (Time limit: M04) | 22.08.2005 | Reply to a communication from the examining division | 07.02.2006 | Communication of intention to grant the patent | 06.06.2006 | Fee for grant paid | 06.06.2006 | Fee for publishing/printing paid | Opposition(s) | 27.04.2007 | No opposition filed within time limit [2007/27] | Fees paid | Renewal fee | 28.08.2003 | Renewal fee patent year 03 | 23.08.2004 | Renewal fee patent year 04 | 18.08.2005 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]GB2016208 (WESTERN ELECTRIC CO) [Y] 1-7,9,10 * figure 2 *; | [Y]JPS56167360 ; | [A]JPS5621359 ; | [A]JPS5799764 ; | [A]JPS60231352 | [Y] - PATENT ABSTRACTS OF JAPAN, (19820410), vol. 0060, no. 55, Database accession no. (E - 101), & JP56167360 A 19811223 (MITSUBISHI ELECTRIC CORP) [Y] 1-7,9,10 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19810512), vol. 0050, no. 70, Database accession no. (E - 056), & JP56021359 A 19810227 (FUJITSU LTD) [A] 1 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19820921), vol. 0061, no. 85, Database accession no. (E - 132), & JP57099764 A 19820621 (TOSHIBA CORP) [A] 1 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19860405), vol. 0100, no. 87, Database accession no. (E - 393), & JP60231352 A 19851116 (FUJITSU KK) [A] 1 * abstract * |