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Extract from the Register of European Patents

EP About this file: EP1204121

EP1204121 - Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  15.12.2006
Database last updated on 26.03.2026
Most recent event   Tooltip12.12.2008Lapse of the patent in a contracting state
New state(s): CY		published on 14.01.2009  [2009/03]
Applicant(s)For all designated states
Broadcom Corporation
16215 Alton Parkway
Irvine, CA 92618 / US
[2006/06]
Former [2002/19]For all designated states
Broadcom Corporation
16215 Alton Parkway
Irvine, California 92618 / US
Inventor(s)01 / Slamowitz, Mark
411 N. Kyrene Road, #148
Chandler, 85226 Arizona / US
02 / Smith, Douglas D.
4021 E. Gable Circle
Mesa, 85206 Arizona / US
03 / Djaja, Gregory
101 W. Briarwood Terrace
Phoenix, 85045 Arizona / US
04 / Knebelsberger, David W.
2116 South Bonarden Lane
Tempe, 85282 Arizona / US
 [2002/27]
Former [2002/19]01 / Slamowitz, Mark
411 N. Kyrene Road, #148
Chandler, 85226 Arizona / US
02 / Smith, Douglas D.
1421 East Gable Circle
Mesa, 85206 Arizona / US
03 / Djaja, Gregory
101 W. Briarwood Terrace
Phoenix, 85045 Arizona / US
04 / Knebelsberger, David W.
2116 South Bonarden Lane
Tempe, 85282 Arizona / US
Representative(s)Jehle, Volker Armin, et al
Bosch Jehle Patentanwaltsgesellschaft mbH
Flüggenstrasse 13
80639 München / DE
[N/P]
Former [2003/22]Jehle, Volker Armin, et al
Patentanwälte Bosch, Graf von Stosch, Jehle, Flüggenstrasse 13
80639 München / DE
Former [2002/19]McLeish, Nicholas Alistair Maxwell, et al
Boult Wade Tennant Verulam Gardens 70 Gray's Inn Road
London WC1X 8BT / GB
Application number, filing date01309366.105.11.2001
[2002/19]
Priority number, dateUS20000245913P03.11.2000         Original published format: US 245913 P
US2001096497127.09.2001         Original published format: US 964971
[2002/19]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1204121
Date:08.05.2002
Language:EN
[2002/19]
Type: A3 Search report 
No.:EP1204121
Date:16.10.2002
[2002/42]
Type: B1 Patent specification 
No.:EP1204121
Date:08.02.2006
Language:EN
[2006/06]
Search report(s)(Supplementary) European search report - dispatched on:EP29.08.2002
ClassificationIPC:G11C11/419, G11C11/412, G11C7/06, G11C7/12
[2002/42]
CPC:
G11C11/419 (EP,US); G11C11/412 (EP,US)
Former IPC [2002/19]G11C11/419, G11C11/412
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2002/19]
TitleGerman:CMOS Speicher (vom Mehrtoregistertyp) mit leistungsreduziertem Spaltenmultiplexierungsschema[2002/19]
English:Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme[2002/19]
French:Mémoire statique CMOS (de type registre multiports) avec schéma de multiplexage de colonnes à puissance réduite[2002/19]
Examination procedure02.12.2002Examination requested  [2003/05]
24.01.2003Despatch of a communication from the examining division (Time limit: M06)
22.07.2003Reply to a communication from the examining division
19.12.2003Despatch of a communication from the examining division (Time limit: M06)
28.05.2004Reply to a communication from the examining division
15.10.2004Despatch of a communication from the examining division (Time limit: M06)
22.03.2005Reply to a communication from the examining division
27.05.2005Communication of intention to grant the patent
06.10.2005Fee for grant paid
06.10.2005Fee for publishing/printing paid
Opposition(s)09.11.2006No opposition filed within time limit [2007/03]
Fees paidRenewal fee
01.12.2003Renewal fee patent year 03
30.11.2004Renewal fee patent year 04
30.11.2005Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT08.02.2006
BE08.02.2006
CH08.02.2006
CY08.02.2006
FI08.02.2006
IT08.02.2006
LI08.02.2006
NL08.02.2006
TR08.02.2006
DK08.05.2006
SE08.05.2006
GR09.05.2006
ES19.05.2006
PT10.07.2006
LU05.11.2006
IE06.11.2006
[2009/03]
Former [2008/37]AT08.02.2006
BE08.02.2006
CH08.02.2006
FI08.02.2006
IT08.02.2006
LI08.02.2006
NL08.02.2006
TR08.02.2006
DK08.05.2006
SE08.05.2006
GR09.05.2006
ES19.05.2006
PT10.07.2006
LU05.11.2006
IE06.11.2006
Former [2008/19]AT08.02.2006
BE08.02.2006
CH08.02.2006
FI08.02.2006
IT08.02.2006
LI08.02.2006
NL08.02.2006
DK08.05.2006
SE08.05.2006
GR09.05.2006
ES19.05.2006
PT10.07.2006
IE06.11.2006
Former [2007/48]AT08.02.2006
BE08.02.2006
CH08.02.2006
FI08.02.2006
IT08.02.2006
LI08.02.2006
NL08.02.2006
DK08.05.2006
SE08.05.2006
ES19.05.2006
PT10.07.2006
IE06.11.2006
Former [2007/36]AT08.02.2006
BE08.02.2006
CH08.02.2006
FI08.02.2006
IT08.02.2006
LI08.02.2006
NL08.02.2006
DK08.05.2006
SE08.05.2006
ES19.05.2006
PT10.07.2006
Former [2007/13]AT08.02.2006
BE08.02.2006
CH08.02.2006
FI08.02.2006
LI08.02.2006
NL08.02.2006
DK08.05.2006
SE08.05.2006
ES19.05.2006
PT10.07.2006
Former [2007/09]AT08.02.2006
CH08.02.2006
FI08.02.2006
LI08.02.2006
NL08.02.2006
DK08.05.2006
SE08.05.2006
ES19.05.2006
PT10.07.2006
Former [2006/51]AT08.02.2006
CH08.02.2006
FI08.02.2006
LI08.02.2006
NL08.02.2006
DK08.05.2006
SE08.05.2006
Former [2006/45]AT08.02.2006
CH08.02.2006
FI08.02.2006
LI08.02.2006
NL08.02.2006
SE08.05.2006
Former [2006/43]AT08.02.2006
CH08.02.2006
FI08.02.2006
LI08.02.2006
Former [2006/42]CH08.02.2006
FI08.02.2006
LI08.02.2006
Former [2006/36]FI08.02.2006
Documents cited:Search[YA] US4771194  (VAN ZEGHBROECK BART J et al.) [Y] 1-39 * figure 2 * * figure 3 * * column 2, line 17 - line 32 * * column 4, line 35 - line 39 * * column 5, line 16 - line 34 * * column 6, line 53 - line 55 * * column 8, line 11 - line 35 *[A] 40
 [YX]   IZUMIKAWA M ET AL: "A CURRENT DIRECTION SENSE TECHNIQUE FOR MULTIPORT SRAM'S", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E79-C, no. 7, 1 July 1996 (1996-07-01), pages 957 - 962, XP000632350, ISSN: 0916-8524 [Y] 1-39 * figure 1 * * page 957, paragraph 1 *[X] 40
Examination  HOFF D. ET AL: "A 23-NS 256K EPROM WITH DOUBLE-LAYER METAL AND ADDRESS TRANSITION DETECTION", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, vol. 24, no. 5, 11 April 1989 (1989-04-11) - 5 October 1989 (1989-10-05), US, pages 1250 - 1258 [A] 40
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.