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EP1256133

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EP About this file: EP1256133

EP1256133 - Method for fabricating a MOS-gated semiconductor device [Right-click to bookmark this link]
Former [2002/46]	MOS-GATED SEMICONDUCTOR DEVICE HAVING ALTERNATING CONDUCTIVITY TYPE SEMICONDUCTOR REGIONS AND METHOD OF MAKING THE SAME
	[2010/23]
Status	No opposition filed within time limit Status updated on 25.11.2011 Database last updated on 20.09.2024
Most recent event Tooltip	06.01.2012	Lapse of the patent in a contracting state	published on 08.02.2012 [2012/06]
Applicant(s)	For all designated states Fairchild Semiconductor Corporation 82 Running Hill Road South Portland, ME 04106 / US
	[2002/46]
Inventor(s)	01 / KOCON, Christopher 16 Grace Drive Plains, PA 18705 / US
	[2002/46]
Representative(s)	Liesegang, Eva Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22 80336 München / DE
	[N/P]
Former [2002/46]	Liesegang, Eva Forrester & Boehmert, Pettenkoferstrasse 20-22 80336 München / DE
Application number, filing date	01906781.8	30.01.2001
	[2002/46]
	WO2001US02964
Priority number, date	US20000502712	11.02.2000 Original published format: US 502712
	[2002/46]
Filing language	EN
Procedural language	EN
Publication	Type:	A2 Application without search report
	No.:	WO0159848
	Date:	16.08.2001
	Language:	EN
	[2001/33]
	Type:	A2 Application without search report
	No.:	EP1256133
	Date:	13.11.2002
	Language:	EN
	The application published by WIPO in one of the EPO official languages on 16.08.2001 takes the place of the publication of the European patent application.
	[2002/46]
	Type:	B1 Patent specification
	No.:	EP1256133
	Date:	19.01.2011
	Language:	EN
	[2011/03]
Search report(s)	International search report - published on:	EP	11.05.2002
Classification	IPC:	H01L21/336, H01L29/78, H01L29/06, H01L29/10, // H01L21/225	[2010/23]
	CPC:	H01L29/7802 (EP,US); H01L21/18 (KR); H01L29/0634 (EP,US); H01L29/7813 (EP,US); H01L29/0649 (EP,US); H01L29/1095 (EP,US)
	Former IPC [2002/46]	H01L29/78, H01L29/10, H01L29/06, H01L21/336, // (H01L29/739, 29:749)
Designated contracting states	DE, FR [2004/22]
Former [2002/46]	AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR
Extension states	AL	Not yet paid
	LT	Not yet paid
	LV	Not yet paid
	MK	Not yet paid
	RO	Not yet paid
	SI	Not yet paid
Title	German:	Verfahren zur Herstellung einer MOS-gesteuerten Halbleiteranordnung	[2010/23]
	English:	Method for fabricating a MOS-gated semiconductor device	[2010/23]
	French:	Méthode de fabrication d'un dispositif semi-conducteur à commande MOS	[2010/23]
	Former [2002/46]	MOS-GESTEUERTE HALBLEITERANORDNUNG MIT HALBLEITERBEREICHEN ABWECHSELNDEN LEITFÄHIGKEITSTYPS UND VERFAHREN ZU DEREN HERSTELLUNG
	Former [2002/46]	MOS-GATED SEMICONDUCTOR DEVICE HAVING ALTERNATING CONDUCTIVITY TYPE SEMICONDUCTOR REGIONS AND METHOD OF MAKING THE SAME
	Former [2002/46]	DISPOSITIFS A DECLENCHEMENT MOS A ALTERNANCE DE ZONES DE CONDUCTIVITE
Entry into regional phase	30.08.2002	National basic fee paid
	30.08.2002	Designation fee(s) paid
	30.08.2002	Examination fee paid
Examination procedure	11.09.2001	Request for preliminary examination filed International Preliminary Examining Authority: EP
	30.08.2002	Examination requested [2002/46]
	03.11.2004	Despatch of a communication from the examining division (Time limit: M04)
	24.02.2005	Reply to a communication from the examining division
	25.04.2007	Despatch of a communication from the examining division (Time limit: M06)
	06.09.2007	Reply to a communication from the examining division
	30.07.2010	Communication of intention to grant the patent
	25.11.2010	Fee for grant paid
	25.11.2010	Fee for publishing/printing paid
Opposition(s)	20.10.2011	No opposition filed within time limit [2011/52]
Fees paid	Renewal fee
	03.04.2003	Renewal fee patent year 03
	26.01.2004	Renewal fee patent year 04
	20.01.2005	Renewal fee patent year 05
	27.01.2006	Renewal fee patent year 06
	29.01.2007	Renewal fee patent year 07
	25.01.2008	Renewal fee patent year 08
	30.01.2009	Renewal fee patent year 09
	25.01.2010	Renewal fee patent year 10
	Penalty fee
	Additional fee for renewal fee
	31.01.2003	03 M06 Fee paid on 03.04.2003
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition Tooltip	FR	21.03.2011
	[2012/06]
Cited in	International search	[X]US5981996 (FUJISHIMA NAOTO [JP]) [X] 1-6 * column 14, line 20 - column 15, line 4; figure 6 *;
		[XA]JPH08264772 ;
		[DXA]US5216275 (CHEN XINGBI [CN]) [DX] 1,3 * column 5, lines 30-38,49-68; figures 2,4,5 * [A] 4;
		[PX]WO0075965 (GEN SEMICONDUCTOR INC [US]) [PX] 1-6 * page 4, line 1 of last paragraph - page 7, line 23; figures 3-7 *;
		[PX]WO0068997 (C P CLARE CORP [US]) [PX] 1-5 * page 10, line 29 - page 12, line 20; figure 6 *;
		[XA] - PATENT ABSTRACTS OF JAPAN, (19970228), vol. 1997, no. 02, & JP08264772 A 19961011 (TOYOTA MOTOR CORP) [X] 1,3 * abstract; paragraphs 0030-0039; figures 5,8,9 * [A] 4-6
		[XA] - CHEN X, "THEORY OF A NOVEL VOLTAGE SUSTAINING (CB) LAYER FOR POWER DEVICES", CHINESE JOURNAL OF ELECTRONICS, TECHNOLOGY EXCHANGE LTD, HONG KONG, HK, (199807), vol. 7, no. 3, ISSN 1022-4653, pages 211 - 216, XP000900759 [X] 1,3 * page 215, lines 14-19 of paragraph IV; figure 4 * [A] 4-6
		[PX] - GLENN J ET AL, "A NOVEL VERTICAL DEEP TRENCH RESURF DMOS (VTR-DMOS)", PROCEEDINGS OF THE 12TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, TOULOUSE, FR, IEEE, PISCATAWAY, NJ, USA, (20000522), pages 197 - 200, XP000974099 [PX] 1-6 * paragraph II; figure 1 *
	Examination	JPH09213939
		- PATENT ABSTRACTS OF JAPAN, (19971225), vol. 1997, no. 12, & JP09213939 A 19970815 (NEC CORP)

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