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Extract from the Register of European Patents

EP About this file: EP1354410

EP1354410 - DIGITAL TO ANALOG CONVERTER EMPLOYING SIGMA-DELTA LOOP AND FEEDBACK DAC MODEL [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  15.02.2008
Database last updated on 11.09.2024
Most recent event   Tooltip11.09.2009Lapse of the patent in a contracting state
New state(s): TR		published on 14.10.2009  [2009/42]
Applicant(s)For all designated states
Teradyne, Inc.
321 Harrison Avenue
Boston, Massachusetts 02118 / US
[2007/15]
Former [2003/43]For all designated states
TERADYNE, INC.
321 Harrison Avenue
Boston, Massachusetts 02118 / US
Inventor(s)01 / SHEEN, Timothy, W.
160 Foster Street
Brighton, MA 02135 / US
 [2003/43]
Representative(s)Luckhurst, Anthony Henry William, et al
Marks & Clerk LLP
90 Long Acre
London
WC2E 9RA / GB
[N/P]
Former [2003/43]Luckhurst, Anthony Henry William, et al
MARKS & CLERK, 57-60 Lincoln's Inn Fields
London WC2A 3LS / GB
Application number, filing date01977178.126.09.2001
[2003/43]
WO2001US30056
Priority number, dateUS2000067606429.09.2000         Original published format: US 676064
[2003/43]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report
No.:WO0227944
Date:04.04.2002
Language:EN
[2002/12]
Type: A2 Application without search report 
No.:EP1354410
Date:22.10.2003
Language:EN
The application published by WIPO in one of the EPO official languages on 04.04.2002 takes the place of the publication of the European patent application.
[2003/43]
Type: B1 Patent specification 
No.:EP1354410
Date:11.04.2007
Language:EN
[2007/15]
Search report(s)International search report - published on:EP14.08.2003
ClassificationIPC:H03M3/04
[2003/43]
CPC:
H03M3/322 (EP,US); H03M1/66 (KR); H03M3/50 (EP,US)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2003/43]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
SINot yet paid
TitleGerman:DIGITAL-ANALOG-WANDLER MIT SIGMA-DELTA SCHLEIFE UND RÜCKKOPPLUNGS-DAW-MODEL[2003/43]
English:DIGITAL TO ANALOG CONVERTER EMPLOYING SIGMA-DELTA LOOP AND FEEDBACK DAC MODEL[2003/43]
French:CONVERTISSEUR NUMERIQUE-ANALOGIQUE UTILISANT UNE BOUCLE SIGMA-DELTA ET UN MODELE DE CAN A RETROACTION[2003/43]
Entry into regional phase28.04.2003National basic fee paid 
28.04.2003Designation fee(s) paid 
28.04.2003Examination fee paid 
Examination procedure24.04.2002Request for preliminary examination filed
International Preliminary Examining Authority: EP
28.04.2003Examination requested  [2003/43]
01.09.2004Despatch of a communication from the examining division (Time limit: M06)
04.03.2005Reply to a communication from the examining division
27.02.2006Despatch of a communication from the examining division (Time limit: M06)
01.09.2006Reply to a communication from the examining division
18.10.2006Communication of intention to grant the patent
22.02.2007Fee for grant paid
22.02.2007Fee for publishing/printing paid
Opposition(s)14.01.2008No opposition filed within time limit [2008/12]
Fees paidRenewal fee
24.09.2003Renewal fee patent year 03
23.09.2004Renewal fee patent year 04
21.09.2005Renewal fee patent year 05
27.09.2006Renewal fee patent year 06
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT11.04.2007
CH11.04.2007
CY11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
TR11.04.2007
SE11.07.2007
GR12.07.2007
ES22.07.2007
PT11.09.2007
GB26.09.2007
LU26.09.2007
MC30.09.2007
[2009/42]
Former [2009/37]AT11.04.2007
CH11.04.2007
CY11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
GR12.07.2007
ES22.07.2007
PT11.09.2007
GB26.09.2007
LU26.09.2007
MC30.09.2007
Former [2009/33]AT11.04.2007
CH11.04.2007
CY11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
GR12.07.2007
ES22.07.2007
PT11.09.2007
GB26.09.2007
MC30.09.2007
Former [2009/03]AT11.04.2007
CH11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
GR12.07.2007
ES22.07.2007
PT11.09.2007
GB26.09.2007
MC30.09.2007
Former [2008/22]AT11.04.2007
CH11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
GR12.07.2007
ES22.07.2007
PT11.09.2007
MC30.09.2007
Former [2008/20]AT11.04.2007
CH11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
GR12.07.2007
ES22.07.2007
PT11.09.2007
Former [2008/08]AT11.04.2007
CH11.04.2007
DK11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
ES22.07.2007
PT11.09.2007
Former [2007/50]AT11.04.2007
CH11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
ES22.07.2007
PT11.09.2007
Former [2007/48]CH11.04.2007
FI11.04.2007
LI11.04.2007
SE11.07.2007
ES22.07.2007
PT11.09.2007
Former [2007/47]ES22.07.2007
Cited inInternational search[Y]US4829236  (BRENARDI ARA [US], et al) [Y] 9,10,19,20 * column 3, line 17 - line 28 *;
 [XY]US4977403  (LARSON LAWRENCE E [US]) [X] 1-5,12-17,22-26 * figure 5 * [Y] 6-11,18-21;
 [Y]EP0457496  (SONY CORP [JP]) [Y] 6-8,18 * figure 3 *;
 [XY]US5101205  (YASUDA AKIRA [JP]) [X] 1-6,12-17,22-26 * column 9, line 54 - line 68; figure 13 * [Y] 7-11,18-21;
 [XY]US5406283  (LEUNG BOSCO [CA]) [X] 1-6,15-17,22-26 * figure 3 * [Y] 7-11,18-21;
 [Y]US5815102  (MELANSON JOHN LAURENCE [US]) [Y] 11,21 * figure 1 *;
 [Y]EP0889599  (SONY CORP [JP]) [Y] 11,21 * figure 1 *;
 [X]  - CATALTEPE T ET AL, "Digitally corrected multi-bit Sigma Delta data converters", IEEE, (19890508), pages 647 - 650, XP010084892 [X] 1-4,6,9,10,15-19 * figure 2 *
 [Y]  - SCHREIER R ET AL, "Noise-shaped multbit D/A convertor employing unit elements", ELECTRONICS LETTERS, IEE STEVENAGE, GB, (19950928), vol. 31, no. 20, ISSN 0013-5194, pages 1712 - 1713, XP006003450 [Y] 7,8,18 * abstract *

DOI:   http://dx.doi.org/10.1049/el:19951194
 [Y]  - COLEMAN J O ET AL, "Vector switching generalizes D/A noise shaping", IEEE JOURNAL, (19990808), vol. 1, pages 478 - 480, XP010510672 [Y] 6-8,18 * figure 2 *
 [Y]  - CARLEY L R, "A NOISE-SHAPING CODER TOPOLOGY FOR 15+ BIT CONVERTERS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, (19890401), vol. 24, no. 2, ISSN 0018-9200, pages 267 - 273, XP000111586 [Y] 6-8,18 * figure 2 *

DOI:   http://dx.doi.org/10.1109/4.18585
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.