blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Release notes
European Patent Register Assistant
European Patent Register Resource Book
European Patent Register – pocket guide
FAQ - European Patent Register
Federated Register (Flyer)
Global Dossier (Flyer)
Register events
Deep link coverage
Federated Register content
The Patent Information Tour
Fair use charter

Extract from the Register of European Patents

EP About this file: EP1274134

EP1274134 - MOS transistor and its fabrication method [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  15.12.2006
Database last updated on 04.11.2024
Most recent event   Tooltip17.10.2008Change - applicantpublished on 19.11.2008  [2008/47]
Applicant(s)For all designated states
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
1006, Oaza Kadoma Kadoma-shi Osaka
571-8501 / JP
[2008/47]
Former [2003/02]For all designated states
Matsushita Electric Industrial Co., Ltd.
1006-banchi, Oaza-Kadoma
Kadoma-shi, Osaka-fu, 571-8501 / JP
Inventor(s)01 / Takagi, Takeshi
3-3, Uzumasa-kitaro-cho, Ukyo-ku
Kyoto-shi, Kyoto 616-8182 / JP
 [2003/02]
Representative(s)Grünecker Patent- und Rechtsanwälte PartG mbB
Leopoldstrasse 4
80802 München / DE
[N/P]
Former [2003/02]Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
Maximilianstrasse 58
80538 München / DE
Application number, filing date02014863.104.07.2002
[2003/02]
Priority number, dateJP2001020293904.07.2001         Original published format: JP 2001202939
[2003/02]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1274134
Date:08.01.2003
Language:EN
[2003/02]
Type: A3 Search report 
No.:EP1274134
Date:02.11.2006
[2006/44]
Search report(s)(Supplementary) European search report - dispatched on:EP02.10.2006
ClassificationIPC:H01L29/78, H01L21/336
[2003/02]
CPC:
H01L29/66651 (EP,US); H01L29/78 (KR); H01L21/76264 (EP,US);
H01L29/41725 (EP,US); H01L29/458 (EP,US); H01L29/78615 (EP,US);
H01L29/78618 (EP,US); H01L29/78639 (EP,US); H01L21/76283 (EP,US);
H01L29/665 (EP,US); H01L29/783 (EP,US) (-)
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   SK,   TR [2003/02]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
SINot yet paid
TitleGerman:MOS Transistor und Verfahren zu dessen Herstellung[2003/02]
English:MOS transistor and its fabrication method[2003/02]
French:Transistor MOS et sa méthode de fabrication[2003/02]
Examination procedure05.12.2006Application withdrawn by applicant  [2007/03]
Fees paidRenewal fee
30.07.2004Renewal fee patent year 03
29.07.2005Renewal fee patent year 04
21.07.2006Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[X]JPH0684939  ;
 [Y]JPH11233771  ;
 [A]GB2185851  (PLESSEY CO PLC) [A] 1-3,6* page 1, line 73 - page 2, line 130; figure - *;
 [Y]US5559368  (HU CHENMING [US], et al) [Y] 9 * abstract *;
 [A]EP0747940  (SGS THOMSON MICROELECTRONICS [US]) [A] 1-6,10,11 * column 6, line 40 - column 8, line 15; figures 1-8 *;
 [XY]EP0782182  (NEC CORP [JP]) [X] 1-6,10-14 * column 6, line 18 - column 7, line 35; figures 2a-2f * [Y] 7,9;
 [X]EP0849804  (TEXAS INSTRUMENTS INC [US]) [X] 1-3,6,10,11 * column 3, line 54 - line 57 * * column 4, lines 47-55 * * column 5, line 35 - column 6, line 6 * * figures 1a-1j *;
 [Y]US5981345  (RYUM BYUNG-RYUL [KR], et al) [Y] 7 * column 4, line 38 - column 5, line 9; figures 3a-3f *;
 [Y]EP1102327  (MATSUSHITA ELECTRIC IND CO LTD [JP]) [Y] 7,9 * paragraph [0080]; figures 3a-6 *;
 [X]  - PATENT ABSTRACTS OF JAPAN, (19940624), vol. 018, no. 336, Database accession no. (E - 1568), & JP06084939 A 19940325 (FUJITSU LTD) [X] 1-6,8,10-14 * abstract * * paragraph [0031] *
 [X]  - "HIGH PERFORMANCE FET STRUCTURE MADE USING MEDIUM TO LOW TEMPERATURE EPITAXY", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, (19910401), vol. 33, no. 11, ISSN 0018-8689, pages 53 - 55, XP000110307 [X] 1-3,6,10,11 * page 53 - page 55; figure - *
 [X]  - IMAI K ET AL, "0.15MUM DELTA-DOPED CMOS WITH ON-FIELD SOURCE/DRAIN CONTACTS", 1996 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS. HONOLULU, JUNE 11 - 13, 1996, SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS, NEW YORK, IEEE, US, (19960611), ISBN 0-7803-3343-8, pages 172 - 173, XP000639315 [X] 12-14 * page 172; figure 1 *

DOI:   http://dx.doi.org/10.1109/VLSIT.1996.507840
 [Y]  - TAKAGI T ET AL, "A Novel High Performance SiGe Channel Heterostructure Dynamic Threshold pMOSFET (HDTMOS)", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, (200105), vol. 22, no. 5, ISSN 0741-3106, XP011018957 [Y] 7,9 * page 206 - page 208; figure 1 *
 [Y]  - PATENT ABSTRACTS OF JAPAN, (19991130), vol. 1999, no. 13, & JP11233771 A 19990827 (MATSUSHITA ELECTRIC IND CO LTD) [Y] 7 * abstract *
 [Y]  - QUINÕNES E ET AL, "Enhanced Mobility PMOSFET's Using Tensile-Strained Si$_{1-y}$C$_y$ Layers", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, (199907), vol. 20, no. 7, ISSN 0741-3106, XP011018617 [Y] 7 * page 338 - page 340; figure 4 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.