Extract from the Register of European Patents

EP About this file: EP1341308

EP1341308 - Phase locked loop [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  01.09.2006
Database last updated on 14.03.2026
Most recent event   Tooltip01.09.2006No opposition filed within time limitpublished on 04.10.2006  [2006/40]
Applicant(s)For all designated states
NIPPON TELEGRAPH AND TELEPHONE CORPORATION
3-1, Otemachi 2-chome, Chiyoda-ku
Tokyo 100-8116 / JP
[N/P]
Former [2005/43]For all designated states
NIPPON TELEGRAPH AND TELEPHONE CORPORATION
3-1, Otemachi 2-chome, Chiyoda-ku
Tokyo 100-8116 / JP
Former [2003/36]For all designated states
Nippon Telegraph and Telephone Corporation
3-1, Otemachi 2-chome, Chiyoda-ku
Tokyo 100-8116 / JP
Inventor(s)01 / Yamagishi, Akihiro, NTT Intellectual Property Cntr
9-11, Midori-chi 3-chome
Musashino-shi, Tokyo 180-8585 / JP
02 / Tsukahara, Tsuneo, NTT Intellectual Property Cntr
9-11, Midori-chi 3-chome
Musashino-shi, Tokyo 180-8585 / JP
 [2003/36]
Representative(s)Rees, Alexander Ellison, et al
Urquhart-Dykes & Lord LLP
30 Welbeck Street
London
WC1G 8ER / GB
[N/P]
Former [2003/36]Rees, Alexander Ellison, et al
Urquhart-Dykes & Lord, 30 Welbeck Street
London W1G 8ER / GB
Application number, filing date02256718.426.09.2002
[2003/36]
Priority number, dateJP2002003056507.02.2002         Original published format: JP 2002030565
[2003/36]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1341308
Date:03.09.2003
Language:EN
[2003/36]
Type: B1 Patent specification 
No.:EP1341308
Date:26.10.2005
Language:EN
[2005/43]
Search report(s)(Supplementary) European search report - dispatched on:EP22.04.2003
ClassificationIPC:H03L7/089, H03L7/14
[2003/36]
CPC:
H03L7/0895 (EP,US); H03L7/14 (EP,US); H03L7/18 (EP,US)
Designated contracting statesDE,   FR,   GB [2004/22]
Former [2003/36]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  SK,  TR 
TitleGerman:Phasenregelschleife[2003/36]
English:Phase locked loop[2003/36]
French:Boucle à verrouillage de phase[2003/36]
Examination procedure10.10.2002Examination requested  [2003/36]
11.05.2004Despatch of a communication from the examining division (Time limit: M04)
21.09.2004Reply to a communication from the examining division
28.04.2005Communication of intention to grant the patent
08.08.2005Fee for grant paid
08.08.2005Fee for publishing/printing paid
Opposition(s)27.07.2006No opposition filed within time limit [2006/40]
Fees paidRenewal fee
09.08.2004Renewal fee patent year 03
26.08.2005Renewal fee patent year 04
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Documents cited:Search[XY] EP1006662  (FUJITSU LTD et al.) [X] 1,2,5-7 * column 21, line 25 - column 21, line 54; figures 1,12 *[Y] 3,8
 [Y] EP0840456  (NEC CORP et al.) [Y] 3,8 * column 13, line 25 - column 14, line 21; figures 6,13 *
 [A] US5675292  (MCCUNE JR EARL W et al.) [A] 1-9 * column 1, line 56 - column 1, line 65; figures 7A,8; claims 1,5 *
 [A] EP0376847  (FUJITSU LTD et al.) [A] 1-9 * column 6, line 13 - column 7, line 21; figures 6,9 *
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