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EP1326290
European procedure
Extract from the Register of European Patents
EP About this file: EP1326290
| EP1326290 - Method of fabricating semiconductor structures [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 25.03.2011 Database last updated on 03.10.2024 | Most recent event Tooltip | 25.03.2011 | No opposition filed within time limit | published on 27.04.2011 [2011/17] | Applicant(s) | For all designated states Xerox Corporation Xerox Square - 20A, 100 Clinton Avenue South Rochester New York 14644 / US | [2010/20] |
| Former [2003/28] | For all designated states Xerox Corporation Xerox Square - 20A, 100 Clinton Avenue South Rochester, New York 14644 / US | Inventor(s) | 01 /
Chua, Christopher L. 636 Curie Drive San Jose, California 95123 / US | 02 /
Kneissl, Michael A. 750 Sylvan Avenue, Apt. 46 Mountain View, California 94041 / US | 03 /
Bour, David P. 11092 Aire Court Cupertino, California 95014 / US | [2003/28] | Representative(s) | Skone James, Robert Edmund Gill Jennings & Every LLP The Broadgate Tower 20 Primrose Street London EC2A 2ES / GB | [N/P] |
| Former [2003/28] | Skone James, Robert Edmund GILL JENNINGS & EVERY Broadgate House 7 Eldon Street London EC2M 7LH / GB | Application number, filing date | 02258579.8 | 12.12.2002 | [2003/28] | Priority number, date | US20010024236 | 21.12.2001 Original published format: US 24236 | [2003/28] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1326290 | Date: | 09.07.2003 | Language: | EN | [2003/28] | Type: | A3 Search report | No.: | EP1326290 | Date: | 15.12.2004 | [2004/51] | Type: | B1 Patent specification | No.: | EP1326290 | Date: | 19.05.2010 | Language: | EN | [2010/20] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.11.2004 | Classification | IPC: | H01L33/00, H01S5/183 | [2004/51] | CPC: |
H01L33/465 (EP,US);
B82Y20/00 (EP,US);
H01L33/0093 (EP,US);
H01S5/18341 (EP,US);
H01L33/105 (EP,US);
H01S5/0213 (EP,US);
H01S5/0215 (EP,US);
H01S5/0217 (EP,US);
H01S5/18369 (EP,US);
H01S5/34333 (EP,US)
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| Former IPC [2003/28] | H01L33/00, H01L21/78, H01L21/20 | Designated contracting states | DE, FR, GB [2005/36] |
| Former [2003/28] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, SI, SK, TR | Title | German: | Verfahren zur Herstellung von Halbleitervorrichtungen | [2003/28] | English: | Method of fabricating semiconductor structures | [2003/28] | French: | Méthode de fabrication de structures semiconductrices | [2003/28] | Examination procedure | 15.06.2005 | Examination requested [2005/33] | 04.05.2006 | Despatch of a communication from the examining division (Time limit: M04) | 06.09.2006 | Reply to a communication from the examining division | 27.06.2007 | Despatch of a communication from the examining division (Time limit: M04) | 07.08.2007 | Reply to a communication from the examining division | 04.12.2009 | Communication of intention to grant the patent | 22.03.2010 | Fee for grant paid | 22.03.2010 | Fee for publishing/printing paid | Opposition(s) | 22.02.2011 | No opposition filed within time limit [2011/17] | Fees paid | Renewal fee | 03.01.2005 | Renewal fee patent year 03 | 02.01.2006 | Renewal fee patent year 04 | 02.01.2007 | Renewal fee patent year 05 | 02.01.2008 | Renewal fee patent year 06 | 05.01.2009 | Renewal fee patent year 07 | 04.01.2010 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0896405 (CANON KK [JP]) [A] 1 * column 11, line 11 - column 12, line 26; figures 7-9 *; | [A]US5877519 (JEWELL JACK L [US]) [A] 8* column 10, line 40 - line 62; figure 6 *; | [X]GB2346478 (AGILENT TECHNOLOGIES INC [US]) [X] 1,2,5-7,9 * page 8, line 5 - page 10, line 22 * * figure 4 * * claim 5 *; | [X]US6320206 (COMAN CARRIE CARTER [US], et al) [X] 1-9 * abstract * * column 5, line 16 - column 8, line 25; figures 3a-3f *; | [A] - MATHINE D L ET AL, "REDUCTION OF THE THERMAL IMPEDANCE OF VERTICAL-CAVITY SURFACE-EMITTING LASERS AFTER INTEGRATION WITH COPPER SUBSTRATES", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, (19960722), vol. 69, no. 4, ISSN 0003-6951, pages 463 - 464, XP000626033 [A] 5 * the whole document * DOI: http://dx.doi.org/10.1063/1.118140 |