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EP1405179
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EP About this file: EP1405179
| EP1405179 - ENHANCING MERGEABILITY OF DATAPATHS AND REDUCING DATAPATH WIDTHS RESPONSIVELY TO REQUIRED PRECISION [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 27.04.2012 Database last updated on 16.04.2026 | Most recent event Tooltip | 27.04.2012 | Application deemed to be withdrawn | published on 30.05.2012 [2012/22] | Applicant(s) | For all designated states Cadence Design Systems, Inc. 2655 Seely Road, MS/5B1 San Jose, CA 95134 / US | For all designated states Mathur, Anmol 4046 Cranford Circle San Jose, CA 95124 / US | [N/P] |
| Former [2004/18] | For all designated states Cadence Design Systems, Inc. 2655 Seely Road, MS/5B1 San Jose, CA 95134 / US | ||
| For all designated states Mathur, Anmol 4046 Cranford Circle San Jose, CA 95124 / US | |||
| Former [2004/15] | For all designated states Cadence Design Systems, Inc. 2655 Seely Road, MS/5B1 San Jose, CA 95134 / US | ||
| For all designated states Saluja, Sanjeev J-65, Sector 25, Jalvayu Vihar 201301 Noida (U.P.) / IN | Inventor(s) | 01 /
SALUJA, Sanjeev J-65, Sector 25, Jalvayu Vihar 201301 Noida (U.P.) / IN | 02 /
MATHUR, Anmol 4046 Cranford Circle san Jose, CA 95124 / US | [2004/18] |
| Former [2004/15] | 01 /
SALUJA, Sanjeev J-65, Sector 25, Jalvayu Vihar 201301 Noida (U.P.) / IN | Representative(s) | Viering, Jentschura & Partner mbB Patent- und Rechtsanwälte Grillparzerstrasse 14 81675 München / DE | [N/P] |
| Former [2004/15] | Viering, Jentschura & Partner Postfach 22 14 43 80504 München / DE | Application number, filing date | 02737524.5 | 17.06.2002 | [2004/15] | WO2002US19139 | Priority number, date | US20010298536P | 15.06.2001 Original published format: US 298536 P | [2004/15] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO02103515 | Date: | 27.12.2002 | Language: | EN | [2002/52] | Type: | A1 Application with search report | No.: | EP1405179 | Date: | 07.04.2004 | Language: | EN | The application published by WIPO in one of the EPO official languages on 27.12.2002 takes the place of the publication of the European patent application. | [2004/15] | Search report(s) | International search report - published on: | US | 27.12.2002 | (Supplementary) European search report - dispatched on: | EP | 30.08.2007 | Classification | IPC: | G06F9/44, G06F17/50 | [2007/40] | CPC: |
G06F8/443 (EP,US);
G06F30/30 (EP,US);
G06F9/44 (EP,US)
|
| Former IPC [2004/15] | G06F9/44 | Designated contracting states | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR [2004/15] | Extension states | AL | Not yet paid | LT | Not yet paid | LV | Not yet paid | MK | Not yet paid | RO | Not yet paid | SI | Not yet paid | Title | German: | VERBESSERUNG DER ZUSAMMENFÜRBARKEIT VON DATENWEGEN UND VERRINGERUNG VON DATENWEGBREITEN ALS REAKTION AUF EINE GEFORDERTE PRÄZISION | [2004/15] | English: | ENHANCING MERGEABILITY OF DATAPATHS AND REDUCING DATAPATH WIDTHS RESPONSIVELY TO REQUIRED PRECISION | [2004/15] | French: | AMELIORATION DE LA CAPACITE DE FUSION DE CHEMINS DE DONNEES ET REDUCTION DE LARGEURS DE CHEMINS DE DONNEES EN REPONSE A UNE PRECISION REQUISE | [2004/15] | Entry into regional phase | 23.12.2003 | National basic fee paid | 23.12.2003 | Search fee paid | 23.12.2003 | Designation fee(s) paid | 23.12.2003 | Examination fee paid | Examination procedure | 14.01.2003 | Request for preliminary examination filed International Preliminary Examining Authority: US | 23.12.2003 | Amendment by applicant (claims and/or description) | 23.12.2003 | Examination requested [2004/15] | 30.05.2011 | Despatch of a communication from the examining division (Time limit: M06) | 10.12.2011 | Application deemed to be withdrawn, date of legal effect [2012/22] | 13.01.2012 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2012/22] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 30.05.2011 | Fees paid | Renewal fee | 04.06.2004 | Renewal fee patent year 03 | 06.06.2005 | Renewal fee patent year 04 | 27.03.2006 | Renewal fee patent year 05 | 08.06.2007 | Renewal fee patent year 06 | 18.03.2008 | Renewal fee patent year 07 | 26.06.2009 | Renewal fee patent year 08 | 25.06.2010 | Renewal fee patent year 09 | 27.06.2011 | Renewal fee patent year 10 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] KUM K-I ET AL: "Word-length optimization for high-level synthesis of digital signal processing systems", SIGNAL PROCESSING SYSTEMS, 1998. SIPS 98. 1998 IEEE WORKSHOP ON CAMBRIDGE, MA, USA 8-10 OCT. 1998, NEW YORK, NY, USA,IEEE, US, 8 October 1998 (1998-10-08), pages 569 - 578, XP010303719, ISBN: 0-7803-4997-0 [A] 1,8 * page 571, line 23 - page 575, line 6 * * figure 2 * DOI: http://dx.doi.org/10.1109/SIPS.1998.715819 | [A] CONSTANTINIDES G A ET AL: "Heuristic datapath allocation for multiple wordlength systems", DESIGN, AUTOMATION AND TEST IN EUROPE, 2001. CONFERENCE AND EXHIBITION 2001. PROCEEDINGS 13-16 MARCH 2001, PISCATAWAY, NJ, USA,IEEE, 13 March 2001 (2001-03-13), pages 791 - 796, XP010538286, ISBN: 0-7695-0993-2 [A] 1,8 * paragraphs [0002] - [02.4] * * figure 2 * | [A] TOGAWA N ET AL: "A high-level synthesis system for digital signal processing based on enumerating data-flow graphs", DESIGN AUTOMATION CONFERENCE 1998. PROCEEDINGS OF THE ASP-DAC '98. ASIA AND SOUTH PACIFIC YOKOHAMA, JAPAN 10-13 FEB. 1998, NEW YORK, NY, USA,IEEE, US, 10 February 1998 (1998-02-10), pages 265 - 274, XP010275930, ISBN: 0-7803-4425-1 [A] 1,8 * page 266, column 2, line 22 - page 267, column 1, line 21 * * page 268, column 1, line 37 - column 2, line 2 * * figure 3 * DOI: http://dx.doi.org/10.1109/ASPDAC.1998.669463 | [PX] MATHUR A ET AL: "Improved merging of datapath operators using information content and required precision analysis", PROCEEDINGS OF THE 38TH. ANNUAL DESIGN AUTOMATION CONFERENCE. (DAC). LAS VEGAS, NV, JUNE 18 - 22, 2001, PROCEEDINGS OF THE DESIGN AUTOMATION CONFERENCE, NEW YORK, NY : ACM, US, vol. CONF. 38, 18 June 2001 (2001-06-18), pages 462 - 467, XP010552432, ISBN: 1-58113-297-2 [PX] 1-16 * the whole document * DOI: http://dx.doi.org/10.1145/378239.378562 | International search | [A] KOCH: "Structured design implementation - a strategy for implementing regular datapath on FPGAs", ACM, 1996, pages 151 - 157, XP002956422 [A] DOI: http://dx.doi.org/10.1145/228370.228392 | [A] RUNDENSTEINER ET AL.: "Functional synthesis using area and delay optimization", IEEE, 1992, pages 291 - 296, XP010028936 [A] DOI: http://dx.doi.org/10.1109/DAC.1992.227790 | [A] KLAUSER ET AL.: "Instruction fetch mechanism for multipath execution processors", IEEE, 1999, pages 38 - 47, XP010364937 [A] DOI: http://dx.doi.org/10.1109/MICRO.1999.809441 | [A] RUDOLPH ET AL.: "Test scheduling and controller synthesis in the CADDY-system", IEEE, 1991, pages 278 - 282, XP002956415 [A] |