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EP1446910
European procedure
Extract from the Register of European Patents
EP Citations: EP1446910
| Cited in | Search | Type: | Patent literature | Publication No.: | US6247138
[Y] (TAMURA HIROTAKA et al.) [Y] 1-12 * column 3, line 21 - line 49 * * column 4, line 33 - line 64 * * column 13, line 54 - column 14, line 8 * * column 25, line 36 - line 57 * * column 25, line 36 - line 57 * * column 28, line 39 - line 49 * * figures 2,8,9,38,55,60 * | Type: | Patent literature | Publication No.: | US6078623
[A] (ISOBE TADAAKI et al.) [A] 1,7 * column 13, line 46 - column 14, line 13; figure 13 * | Type: | Non-patent literature | Publication information: | [Y] NATSUKI KUSHIYAMA: "A 500-MEGABYTE/S DATA-RATE 4.5M DRAM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 28, no. 4, 1 April 1993 (1993-04-01), pages 490 - 498, XP000362979, ISSN: 0018-9200 [Y] 1-12 * page 493, column R, paragraph 3 - page 494, column L, paragraph 1 * * figures 6,7 * | DOI: | http://dx.doi.org/10.1109/4.210033 | Type: | Non-patent literature | Publication information: | [Y] YIDO KOO ET AL: "A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method", VLSI AND CAD, 1999. ICVC '99. 6TH INTERNATIONAL CONFERENCE ON SEOUL, SOUTH KOREA 26-27 OCT. 1999, PISCATAWAY, NJ, USA,IEEE, US, 26 October 1999 (1999-10-26), pages 339 - 341, XP010370138, ISBN: 0-7803-5727-2 [Y] 1-12 * page 339, column L, paragraph 2; figures 4,5 * * page 340, column L, line 1 - column R, line 2 * | DOI: | http://dx.doi.org/10.1109/ICVC.1999.820925 | Type: | Non-patent literature | Publication information: | [A] "SLDRAM ARCHITECTURAL AND FUNCTIONAL OVERVIEW", SLDRAM ARCHITECTURAL AND FUNCTIONAL OVERVIEW, August 1997 (1997-08-01), pages 1 - 14, XP002101005 [A] 1,7 * page 10, paragraphs SLDRAM,CALIBRATION - page 11 * | Type: | Non-patent literature | Publication information: | [A] JOONBAE PARK ET AL: "A semi-digital delay locked loop for clock skew minimization", VLSI DESIGN, 1999. PROCEEDINGS. TWELFTH INTERNATIONAL CONFERENCE ON GOA, INDIA 7-10 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 7 January 1999 (1999-01-07), pages 584 - 588, XP010319965, ISBN: 0-7695-0013-7 [A] 1,7 * page 586, column R, paragraph 2.2 - page 587; figures 2,8 * | Type: | Non-patent literature | Publication information: | [A] "BINARLY WEIGHTED ELEMENT PULSE DELAY LINE", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 39, no. 6, June 1996 (1996-06-01), pages 153 - 154, XP000678555, ISSN: 0018-8689 [A] 1,7 * the whole document * | Cited in | Examination | Type: | Patent literature | Publication No.: | US6047346
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