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EP1359768
European procedure
Extract from the Register of European Patents
EP Citations: EP1359768
| Cited in | Search | Type: | Patent literature | Publication No.: | US5659365
[X] (WILKINSON JAMES HEDLEY [GB]) [X] 1,2,9-12,18,22,23,26,27,30 * column 2, line 19 - line 49 * * column 2, line 66 - column 4, line 67 *; | Type: | Patent literature | Publication No.: | EP0884912
[YX] (HITACHI LTD [JP]) [Y] 1-8,22-25 * page 4, line 14 - line 27 * * page 5, line 16 - page 6, line 53 * * page 9, line 25 - page 10, line 30 * [X] 9-13,15,17,18,20,21,26,27,30; | Type: | Non-patent literature | Publication information: | [Y] - YANG K-M ET AL, "Very high efficiency VLSI chip-pair for full search block matching with fractional precision", PROC. ICASSP, IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, GLASGOW, UK, (19890523), pages 2437 - 2440, XP010083029 [Y] 1-8,22-25 * page 2438, paragraph 3 * | Type: | Non-patent literature | Publication information: | [A] - MASAHIRO IWAHASHI ET AL, "A MOTION COMPENSATION TECHNIQUE FOR DOWN-SCALED PICTURES IN LAYERED CODING", IEICE TRANSACTIONS ON COMMUNICATIONS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, (19940801), vol. E77-B, no. 8, ISSN 0916-8516, pages 1007 - 1012, XP000470652 [A] 1-32 * page 1008, paragraph 3 - page 1011, paragraph 4.2 * |