EP1353386 - Control method for insulated gate thin film transistor [Right-click to bookmark this link] | |||
Former [2003/42] | Insulated gate thin film transistor and control system therefor | ||
[2017/01] | Status | No opposition filed within time limit Status updated on 14.12.2018 Database last updated on 22.08.2024 | |
Former | The patent has been granted Status updated on 05.01.2018 | ||
Former | Grant of patent is intended Status updated on 21.08.2017 | ||
Former | Examination is in progress Status updated on 16.05.2017 | ||
Former | Grant of patent is intended Status updated on 08.01.2017 | Most recent event Tooltip | 11.01.2019 | Change - classification | published on 13.02.2019 [2019/07] | Applicant(s) | For all designated states ABLIC Inc. 1-8, Nakase Mihama-ku Chiba-shi Chiba 261-8507 / JP | For all designated states Hayashi, Yutaka 3-10, Umezono 2-chome Tsukuba-shi Ibaraki / JP | [2018/18] |
Former [2016/17] | For all designated states SII Semiconductor Corporation 8 Nakase 1-chome Mihama-ku Chiba-shi, Chiba 261-8507 / JP | ||
For all designated states Hayashi, Yutaka 3-10, Umezono 2-chome Tsukuba-shi Ibaraki / JP | |||
Former [2003/42] | For all designated states Seiko Instruments Inc. 8, Nakase 1-chome, Mihama-ku Chiba-shi, Chiba / JP | ||
For all designated states Hayashi, Yutaka 3-10, Umezono 2-chome Tsukuba-shi, Ibaraki / JP | Inventor(s) | 01 /
Hayashi, Yutaka 3-10 Umezono 2-chome Tsukuba-shi, Ibaraki / JP | 02 /
Hasegawa, Hisashi@c/o Seiko Instruments Inc. 8 Nakase 1-chome Mihama-ku Chiba-shi, Chiba / JP | 03 /
Yoshida, Yoshifumi@c/o Seiko Instruments Inc. 8 Nakase 1-chome Mihama-ku Chiba-shi, Chiba / JP | 04 /
Osanai, Jun@c/o Seiko Instruments Inc. 8 Nakase 1-chome Mihama-ku Chiba-shi, Chiba / JP | [2018/06] |
Former [2003/42] | 01 /
Hayashi, Yutaka 3-10 Umezono 2-chome Tsukuba-shi, Ibaraki / JP | ||
02 /
Hasegawa, Hisashi, c/o Seiko Instruments Inc. 8 Nakase 1-chome, Mihama-ku Chiba-shi, Chiba / JP | |||
03 /
Yoshida, Yoshifumi, c/o Seiko Instruments Inc. 8 Nakase 1-chome, Mihama-ku Chiba-shi, Chiba / JP | |||
04 /
Osanai, Jun, c/o Seiko Instruments Inc. 8 Nakase 1-chome, Mihama-ku Chiba-shi, Chiba / JP | Representative(s) | Miller Sturt Kenyon 9 John Street London WC1N 2ES / GB | [2018/06] |
Former [2003/42] | Sturt, Clifford Mark, et al Miller Sturt Kenyon 9 John Street London WC1N 2ES / GB | Application number, filing date | 03252252.6 | 09.04.2003 | [2003/42] | Priority number, date | JP20020108422 | 10.04.2002 Original published format: JP 2002108422 | [2003/42] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1353386 | Date: | 15.10.2003 | Language: | EN | [2003/42] | Type: | A3 Search report | No.: | EP1353386 | Date: | 15.09.2004 | [2004/38] | Type: | B1 Patent specification | No.: | EP1353386 | Date: | 07.02.2018 | Language: | EN | [2018/06] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 03.08.2004 | Classification | IPC: | H01L29/786, H01L27/12 | [2004/38] | CPC: |
H01L29/78615 (EP,US);
H01L21/18 (KR);
H01L21/84 (EP,US);
H01L27/1203 (EP,US)
|
Former IPC [2003/42] | H01L29/786, H01L21/336 | Designated contracting states | FR, NL [2018/06] |
Former [2005/22] | FR, NL | ||
Former [2003/42] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR | Title | German: | Steuermethode für Dünnfilmtransistor mit isoliertem Gate | [2017/01] | English: | Control method for insulated gate thin film transistor | [2017/01] | French: | Méthode de contrôle d'un transistor à couche mince à grille isolée | [2017/01] |
Former [2003/42] | Dünnfilmtransistor mit isoliertem Gate und diesbezügliches Kontrollsystem | ||
Former [2003/42] | Insulated gate thin film transistor and control system therefor | ||
Former [2003/42] | Transistor à couche mince à grille isolée et son système de contrôle | Examination procedure | 28.02.2005 | Examination requested [2005/17] | 03.03.2005 | Amendment by applicant (claims and/or description) | 21.04.2008 | Despatch of a communication from the examining division (Time limit: M04) | 28.08.2008 | Reply to a communication from the examining division | 09.06.2010 | Despatch of a communication from the examining division (Time limit: M06) | 17.12.2010 | Reply to a communication from the examining division | 22.02.2013 | Despatch of a communication from the examining division (Time limit: M04) | 27.06.2013 | Reply to a communication from the examining division | 29.10.2015 | Despatch of a communication from the examining division (Time limit: M04) | 04.03.2016 | Reply to a communication from the examining division | 30.11.2016 | Cancellation of oral proceeding that was planned for 01.12.2016 | 01.12.2016 | Date of oral proceedings (cancelled) | 09.01.2017 | Communication of intention to grant the patent | 08.05.2017 | Disapproval of the communication of intention to grant the patent by the applicant or resumption of examination proceedings by the EPO | 22.08.2017 | Communication of intention to grant the patent | 21.12.2017 | Fee for grant paid | 21.12.2017 | Fee for publishing/printing paid | 21.12.2017 | Receipt of the translation of the claim(s) | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 21.04.2008 | Opposition(s) | 08.11.2018 | No opposition filed within time limit [2019/03] | Fees paid | Renewal fee | 13.04.2005 | Renewal fee patent year 03 | 17.03.2006 | Renewal fee patent year 04 | 12.04.2007 | Renewal fee patent year 05 | 28.03.2008 | Renewal fee patent year 06 | 16.04.2009 | Renewal fee patent year 07 | 25.03.2010 | Renewal fee patent year 08 | 12.04.2011 | Renewal fee patent year 09 | 28.03.2012 | Renewal fee patent year 10 | 12.04.2013 | Renewal fee patent year 11 | 25.03.2014 | Renewal fee patent year 12 | 10.04.2015 | Renewal fee patent year 13 | 30.03.2016 | Renewal fee patent year 14 | 10.04.2017 | Renewal fee patent year 15 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]WO9927585 (HITACHI LTD [JP], et al) [X] 1-21 * abstract *; | [X]EP1143527 (SHARP KK [JP]) [X] 1-3,11,13,14,20 * column 5, line 37 - column 7, line 11 * * column 7, line 54 - column 8, line 17 * * column 9, line 11 - line 41 *; | [PX]US6392277 (MITANI SHINICHIRO [JP], et al) [PX] 1-21 * column 3, line 1 - column 4, line 18 * * column 5, line 18 - column 6, line 20 * * column 7, line 51 - column 9, line 28 ** column 15, line 55 - column 19, line 63; figure -; claim - *; | [A] - CASU M R ET AL, "Comparative analysis of PD-SOI active body-biasing circuits", 2000 IEEE INTERNATIONAL SOI CONFERENCE. PROCEEDINGS, WAKEFIELD, MA, USA, (20001002), ISBN 0-7803-6389-2, pages 94 - 95, XP002289022 [A] 1-21 * the whole document * DOI: http://dx.doi.org/10.1109/SOI.2000.892786 | [A] - KISTLER N ET AL, "Symmetric CMOS in fully-depleted silicon-on-insulator using P<+>-polycrystalline SiGe gate electrodes", ELECTRON DEVICES MEETING, 1993. TECHNICAL DIGEST., INTERNATIONAL WASHINGTON, DC, USA 5-8 DEC. 1993, NEW YORK, NY, USA,IEEE, (19931205), ISBN 0-7803-1450-6, pages 727 - 730, XP010118301 [A] 17-19 * the whole document * DOI: http://dx.doi.org/10.1109/IEDM.1993.347210 | by applicant | WO9927585 |