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Extract from the Register of European Patents

EP About this file: EP1357433

EP1357433 - Method of fabricating sub-lithographic sized line and space patterns [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  05.05.2006
Database last updated on 02.09.2024
Most recent event   Tooltip15.08.2008Change - applicantpublished on 17.09.2008  [2008/38]
Applicant(s)For all designated states
Hewlett-Packard Company
3000 Hanover Street
Palo Alto, CA 94304-1112 / US
[N/P]
Former [2008/38]For all designated states
Hewlett-Packard Company
3000 Hanover Street
Palo Alto CA 94304-1112 / US
Former [2003/44]For all designated states
Hewlett-Packard Company
3000 Hanover Street
Palo Alto, CA 94304 / US
Inventor(s)01 / Lee, Heon
Gyosu APT 6-602, Jong-dong, Nam-Gu, Pohang-Si
Kyungbuk, Korea Zip 790-751 / KR
 [2003/48]
Former [2003/44]01 / Lee, Heon
455 Brahms Way, Apt 230
Sunnyvale, CA 94087 / US
Representative(s)Tollett, Ian, et al
Williams Powell
44 Prespect Place
Bromley, Kent BR2 9HN / GB
[N/P]
Former [2003/44]Tollett, Ian, et al
Williams Powell Morley House 26-30 Holborn Viaduct
London EC1A 2BP / GB
Application number, filing date03252487.817.04.2003
[2003/44]
Priority number, dateUS2002013377223.04.2002         Original published format: US 133772
[2003/44]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1357433
Date:29.10.2003
Language:EN
[2003/44]
Type: A3 Search report 
No.:EP1357433
Date:23.06.2004
[2004/26]
Search report(s)(Supplementary) European search report - dispatched on:EP12.05.2004
ClassificationIPC:G03F7/20, G03F7/00, H01L21/033
[2004/25]
CPC:
B82Y10/00 (EP,US); G03F7/0002 (EP,US); B82Y40/00 (EP,US);
G03F7/0017 (EP,US); H01L21/0338 (EP,US); H01L21/31144 (EP,US);
H01L21/32139 (EP,US) (-)
Former IPC [2003/44]G03F7/20
Designated contracting statesFR,   GB [2005/11]
Former [2003/44]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:Verfahren zur Herstellung sublithographischer Linien- und Raummuster[2003/44]
English:Method of fabricating sub-lithographic sized line and space patterns[2003/44]
French:Méthode pour la fabrication de motifs de lignes et d'espacements de taille sous-lithographique[2005/32]
Former [2003/44]Méthode pour la fabrication de motifs de linéaires ou spatiales sous-lithographiques
Examination procedure09.08.2004Examination requested  [2004/41]
27.12.2004Loss of particular rights, legal effect: designated state(s)
14.04.2005Despatch of communication of loss of particular rights: designated state(s) DE, IT
08.07.2005Communication of intention to grant the patent
19.11.2005Application deemed to be withdrawn, date of legal effect  [2006/23]
13.01.2006Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time  [2006/23]
Fees paidRenewal fee
20.04.2005Renewal fee patent year 03
Penalty fee
Penalty fee Rule 85a EPC 1973
31.01.2005DE   M01   Not yet paid
31.01.2005IT   M01   Not yet paid
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]JPS62247530  ;
 [A]JPH01189923  ;
 [A]DE4236609  (SIEMENS AG [DE]) [A] 1-10 * column 1 * * column 3, line 49 - column 4, line 11; figures 1-4 *;
 [A]US5795830  (CRONIN JOHN E [US], et al) [A] 1-10 * the whole document *;
 [A]US5998287  (HUANG HENG SHENG [TW]) [A] 1-10 * the whole document *;
 [A]  - PATENT ABSTRACTS OF JAPAN, (19880413), vol. 012, no. 118, Database accession no. (E - 600), & JP62247530 A 19871028 (FUJITSU LTD) [A] 1-10 * abstract *
 [A]  - ANONYMOUS, "Extending the Minimal Dimensions of Photolithographic Integrated Circuit Fabrication Processing. September 1977.", IBM TECHNICAL DISCLOSURE BULLETIN, New York, US, (19770901), vol. 20, no. 4, pages 1376 - 1378, XP002277678 [A] 1-10 * the whole document *
 [A]  - TSUTSUMI T ET AL, "FABRICATION TECHNOLOGY OF ULTRAFINE SIO2 MASKS AND SI NANOWIRES USING OXIDATION OF VERTICAL SIDEWALLS OF A POLY-SI LAYER", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, (199901), vol. 17, no. 1, ISSN 0734-211X, pages 77 - 81, XP000804175 [A] 1-10 * figure 1 *

DOI:   http://dx.doi.org/10.1116/1.590538
 [A]  - PATENT ABSTRACTS OF JAPAN, (19891031), vol. 013, no. 481, Database accession no. (E - 838), & JP01189923 A 19890731 (NEC CORP) [A] 1-10 * abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.