| EP1505656 - Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.11.2007 Database last updated on 11.04.2026 | Most recent event Tooltip | 25.01.2008 | Lapse of the patent in a contracting state | published on 27.02.2008 [2008/09] | Applicant(s) | For all designated states STMicroelectronics Srl Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | [N/P] |
| Former [2005/06] | For all designated states STMicroelectronics S.r.l. Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | Inventor(s) | 01 /
Pellizzer, Fabio Via Peroz, 16 31051 Follina / IT | 02 /
Bez, Roberto Via Vespri Siciliani, 2 20146 Milano / IT | [2005/06] | Representative(s) | Cerbaro, Elena, et al Studio Torta S.p.A. Via Viotti, 9 10121 Torino / IT | [N/P] |
| Former [2005/06] | Cerbaro, Elena, Dr., et al STUDIO TORTA S.r.l., Via Viotti, 9 10121 Torino / IT | Application number, filing date | 03425536.4 | 05.08.2003 | [2005/06] | Filing language | IT | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1505656 | Date: | 09.02.2005 | Language: | EN | [2005/06] | Type: | B1 Patent specification | No.: | EP1505656 | Date: | 03.01.2007 | Language: | EN | [2007/01] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.03.2004 | Classification | IPC: | H01L27/24 | [2005/06] | CPC: |
H10B63/32 (EP,US);
H10B63/82 (EP,US);
H10N70/068 (EP,US);
H10N70/231 (EP,US);
H10N70/826 (EP,US);
H10N70/8413 (EP,US);
H10N70/8828 (EP,US)
(-)
| Designated contracting states | DE, FR, GB, IT [2005/43] |
| Former [2005/06] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR | Title | German: | Verfahren zur Herstellung einer Anordnung von Phasenwechselspeichern in Kupfer-Damaszenertechnologie sowie entsprechend hergestellte Anordnungen von Phasenwechselspeichern | [2005/06] | English: | Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby | [2005/06] | French: | Procédé de fabrication d'un arrangement de mémoires à changement de phase par damasquinage du cuivre et arrangement de mémoires à changement de phase ainsi fabriqué | [2005/06] | Examination procedure | 28.07.2005 | Examination requested [2005/38] | 06.09.2005 | Despatch of a communication from the examining division (Time limit: M06) | 16.03.2006 | Reply to a communication from the examining division | 11.07.2006 | Communication of intention to grant the patent | 07.11.2006 | Fee for grant paid | 07.11.2006 | Fee for publishing/printing paid | Opposition(s) | 05.10.2007 | No opposition filed within time limit [2007/50] | Fees paid | Renewal fee | 30.08.2005 | Renewal fee patent year 03 | 31.08.2006 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | DE | 04.04.2007 | [2008/09] | Documents cited: | Search | [XY] US2002080647 (CHIANG CHIEN et al.) [X] 1,12-14,16 * paragraphs [0002] , [0007] , [0025] * * paragraph [0041] - paragraph [0051] * * figures 1,13A,15 *[Y] 1-10,15 | [Y] US5933365 (KLERSY PATRICK et al.) [Y] 1-10,15 * column 10, line 29 - column 17, line 40; figure 1A * | [XY] US5869843 (HARSHFIELD STEVEN T et al.) [X] 1,12,13 * column 1, line 4 - column 5, line 57 *[Y] 2 | [DX] EP1318552 (ST MICROELECTRONICS SRL et al.) [DX] 13,16 * paragraph [0050]; figures 22,25 * | [XY] EP1326254 (ST MICROELECTRONICS SRL et al.) [X] 13 * paragraphs [0034] , [0035] *[Y] 3 |