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EP1504533
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EP About this file: EP1504533
| EP1504533 - PROCESSING METHOD AND APPARATUS FOR IMPLEMENTING SYSTOLIC ARRAYS [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 09.03.2018 Database last updated on 01.10.2024 | |
| Former | Examination is in progress Status updated on 29.11.2017 | Most recent event Tooltip | 11.01.2019 | Change - classification | published on 13.02.2019 [2019/07] | Applicant(s) | For all designated states Intel Corporation 2200 Mission College Boulevard Santa Clara, CA 95054 / US | [N/P] |
| Former [2014/12] | For all designated states Intel Corporation 2200 Mission College Boulevard Santa Clara, CA 95054 / US | ||
| Former [2009/35] | For all designated states Silicon Hive B.V. High Tech Campus 83 5656 AG Eindhoven / NL | ||
| Former [2009/03] | For all designated states Silicon Hive B.V. High Tech Campus 43 5656 AE Eindhoven / NL | ||
| Former [2005/06] | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | Inventor(s) | 01 /
DE OLIVEIRA KASTRUP PEREIRA, Bernardo Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | [2005/06] | Representative(s) | V.O. P.O. Box 87930 2508 DH Den Haag / NL | [N/P] |
| Former [2009/35] | Hatzmann, Martin, et al Vereenigde Johan de Wittlaan 7 2517 JR Den Haag / NL | ||
| Former [2007/41] | Hatzmann, Martin VEREENIGDE Johan de Wittlaan 7 2517 JR Den Haag / NL | ||
| Former [2005/06] | Eleveld, Koop Jan Philips Intellectual Property & Standards, P.O. Box 220 5600 AE Eindhoven / NL | Application number, filing date | 03708428.2 | 01.04.2003 | [2005/06] | WO2003IB01187 | Priority number, date | EP20020076649 | 25.04.2002 Original published format: EP 02076649 | [2005/06] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | WO03092171 | Date: | 06.11.2003 | Language: | EN | [2003/45] | Type: | A2 Application without search report | No.: | EP1504533 | Date: | 09.02.2005 | Language: | EN | The application published by WIPO in one of the EPO official languages on 06.11.2003 takes the place of the publication of the European patent application. | [2005/06] | Search report(s) | International search report - published on: | EP | 21.10.2004 | Classification | IPC: | H04B1/00 | [2005/06] | CPC: |
G06F15/8046 (EP,US);
G06F7/00 (KR)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR [2005/06] | Extension states | AL | Not yet paid | LT | Not yet paid | LV | Not yet paid | MK | Not yet paid | Title | German: | VERARBEITUNGSVERFAHREN UND VORRICHTUNG ZUR IMPLEMENTIERUNG VON SYSTOLISCHEN GATTERPROZESSOREN | [2005/06] | English: | PROCESSING METHOD AND APPARATUS FOR IMPLEMENTING SYSTOLIC ARRAYS | [2005/06] | French: | PROCEDE DE TRAITEMENT ET APPAREIL DE CONCEPTION DE RESEAUX SYSTOLIQUES | [2005/06] | Entry into regional phase | 25.11.2004 | National basic fee paid | 21.04.2005 | Designation fee(s) paid | 21.04.2005 | Examination fee paid | Examination procedure | 21.04.2005 | Examination requested [2005/25] | 27.08.2007 | Despatch of a communication from the examining division (Time limit: M04) | 14.12.2007 | Reply to a communication from the examining division | 26.05.2011 | Despatch of a communication from the examining division (Time limit: M06) | 01.12.2011 | Reply to a communication from the examining division | 03.11.2017 | Application deemed to be withdrawn, date of legal effect [2018/15] | 30.11.2017 | Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time [2018/15] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 27.08.2007 | Fees paid | Renewal fee | 02.05.2005 | Renewal fee patent year 03 | 02.05.2006 | Renewal fee patent year 04 | 02.05.2007 | Renewal fee patent year 05 | 17.03.2008 | Renewal fee patent year 06 | 15.04.2009 | Renewal fee patent year 07 | 16.04.2010 | Renewal fee patent year 08 | 15.04.2011 | Renewal fee patent year 09 | 19.04.2012 | Renewal fee patent year 10 | 18.03.2013 | Renewal fee patent year 11 | 25.03.2014 | Renewal fee patent year 12 | 10.04.2015 | Renewal fee patent year 13 | 11.04.2016 | Renewal fee patent year 14 | Penalty fee | Additional fee for renewal fee | 30.04.2017 | 15 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [XA]EP0717347 (MOTOROLA INC [US]) [X] 1-3,5,7 * abstract * * column 6, line 37 - column 10, line 47; figure 3 * [A] 11; | [A]EP0729106 (NOKIA MOBILE PHONES LTD [FI]) [A] 4,11 * column 5, line 54 - column 6, line 27 *; | [DA] - ZAPATA E L ET AL, "A VLSI CONSTANT GEOMETRY ARCHITECTURE FOR THE FAST HARTLEY AND FOURIER TRANSFORMS", IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, IEEE INC, NEW YORK, US, (1992), vol. 3, no. 1, ISSN 1045-9219, pages 58 - 70, XP000262132 [DA] 1,11 * the whole document * DOI: http://dx.doi.org/10.1109/71.113082 | by applicant | EP1113357 |