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EP1552653
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EP About this file: EP1552653
| EP1552653 - INTEGRATED CIRCUIT AND METHOD FOR ESTABLISHING TRANSACTIONS [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 31.08.2007 Database last updated on 28.03.2026 | Most recent event Tooltip | 31.08.2007 | Application deemed to be withdrawn | published on 03.10.2007 [2007/40] | Applicant(s) | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
| Former [2005/28] | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | Inventor(s) | 01 /
RADULESCU, Andrei c/o Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | [2005/28] | Representative(s) | Eleveld, Koop Jan Philips Intellectual Property & Standards High Tech Campus 5 5656 AE Eindhoven / NL | [N/P] |
| Former [2005/28] | Eleveld, Koop Jan Philips Intellectual Property & Standards, P.O. Box 220 5600 AE Eindhoven / NL | Application number, filing date | 03748421.9 | 07.10.2003 | [2005/28] | WO2003IB04401 | Priority number, date | EP20020079196 | 08.10.2002 Original published format: EP 02079196 | EP20030101095 | 22.04.2003 Original published format: EP 03101095 | [2005/28] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2004034652 | Date: | 22.04.2004 | Language: | EN | [2004/17] | Type: | A1 Application with search report | No.: | EP1552653 | Date: | 13.07.2005 | Language: | EN | The application published by WIPO in one of the EPO official languages on 22.04.2004 takes the place of the publication of the European patent application. | [2005/28] | Search report(s) | International search report - published on: | EP | 22.04.2004 | Classification | IPC: | H04L12/56, H04L29/06, H04L12/28 | [2005/28] | CPC: |
H04L65/611 (EP,US);
H04L12/18 (KR,US);
H04L12/1886 (EP);
H04L65/1069 (EP);
H04L65/765 (EP);
H04L9/40 (US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR [2005/28] | Extension states | AL | Not yet paid | LT | Not yet paid | LV | Not yet paid | MK | Not yet paid | Title | German: | INTEGRIERTE SCHALTUNG UND VERFAHREN ZUR ERSTELLUNG VON TRANSAKTIONEN | [2005/28] | English: | INTEGRATED CIRCUIT AND METHOD FOR ESTABLISHING TRANSACTIONS | [2005/28] | French: | CIRCUIT INTEGRE ET PROCEDE PERMETTANT L'ETABLISSEMENT DE TRANSACTIONS | [2005/28] | Entry into regional phase | 09.05.2005 | National basic fee paid | 09.05.2005 | Designation fee(s) paid | 09.05.2005 | Examination fee paid | Examination procedure | 09.05.2005 | Examination requested [2005/28] | 16.11.2005 | Despatch of a communication from the examining division (Time limit: M04) | 13.03.2006 | Reply to a communication from the examining division | 11.10.2006 | Despatch of a communication from the examining division (Time limit: M04) | 22.02.2007 | Application deemed to be withdrawn, date of legal effect [2007/40] | 14.05.2007 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2007/40] | Fees paid | Renewal fee | 31.10.2005 | Renewal fee patent year 03 | 31.10.2006 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [Y] [online] S KUMAR ET AL: "A Network on Chip Architecture and Design Methodology", XP002263346, retrieved from CSDL.COMPUTER.ORG/COMP/PROCEEDINGS/ISVLSI/2002/148 [Y] 1-9 * page 1, column R, line 11 - page 2, column R, line 14 * * page 3, column L, line 13 - page 6, column L, line 27; figures 1-4 * DOI: http://dx.doi.org/10.1109/ISVLSI.2002.1016885 | [YA] GUERRIER P ET AL: "A Generic Architecture for On-Chip Packet-Switched Interconnections", 27 March 2000 (2000-03-27), pages 250 - 256, XP010377472 [Y] 1-3,8,9 * page 251, column L, line 10 - page 253, column R, line 17 * * page 254, column R, line 1 - line 54; figures 2-8 * [A] 4-7 | [YA] MOON SANG-JUN ET AL: "Scalable and reliable ATM multicast employing RM cell consolidation", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 35, no. 23, 11 November 1999 (1999-11-11), pages 2008 - 2009, XP006012937, ISSN: 0013-5194 [Y] 1-3,8,9 * page 1, column L, line 1 - column R, line 38 *[A] 4-7 DOI: http://dx.doi.org/10.1049/el:19991360 |