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EP1473644
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EP About this file: EP1473644
| EP1473644 - A method for mapping a logic circuit to a programmable look up table [Right-click to bookmark this link] | Status | The application has been refused Status updated on 02.11.2012 Database last updated on 18.11.2024 | Most recent event Tooltip | 02.11.2012 | Refusal of application | published on 05.12.2012 [2012/49] | Applicant(s) | For all designated states Sicronic Remote KG, LLC 1209 Orange Street Wilmington, DE 19801 / US | [2008/15] |
| Former [2008/01] | For all designated states STMicroelectronics Pvt. Ltd. Plot No. 1, Knowledge Park III 201308 Greater Noida, Uttar Pradesh / IN | ||
| Former [2004/45] | For all designated states STMicroelectronics Pvt. Ltd Plot No. 2 & 3, Sector 16A, Institutional Area Noida 201 301, Uttar Pradesh / IN | Inventor(s) | 01 /
Sharma, Sunil Kumar A312, Sector 19 Noida, UP - 201 301 / IN | 02 /
Tomar, Ajay A312, Sector 19 Noida, UP - 201 301 / IN | 03 /
Samanta, Dhabalendu B4/7, Glaxo Apats., Mayur Vihar, Phase-l, Extn. Delhi - 110 091 / IN | [2004/45] | Representative(s) | Kazi, Ilya Mathys & Squire The Shard 32 London Bridge Street London SE1 9SG / GB | [N/P] |
| Former [2010/22] | Kazi, Ilya Mathys & Squire LLP 120 Holborn London EC1N 2SQ / GB | ||
| Former [2010/18] | Griffin, Philippa Jane Mathys & Squire LLP 120 Holborn London EC1N 2SQ / GB | ||
| Former [2008/45] | Cerbaro, Elena, et al STUDIO TORTA Via Viotti 9 10121 Torino / IT | ||
| Former [2004/45] | Cerbaro, Elena, et al c/o Studio Torta S.r.l. Via Viotti, 9 10121 Torino / IT | Application number, filing date | 04009701.6 | 23.04.2004 | [2004/45] | Priority number, date | IN2003DEL0632 | 25.04.2003 Original published format: IN de06322003 | [2004/45] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1473644 | Date: | 03.11.2004 | Language: | EN | [2004/45] | Type: | A3 Search report | No.: | EP1473644 | Date: | 21.09.2005 | [2005/38] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.08.2005 | Classification | IPC: | G06F17/50 | [2004/45] | CPC: |
G06F30/34 (EP,US)
| Designated contracting states | DE, FR, GB, IT [2006/23] |
| Former [2004/45] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Verfahren zur Abbildung eines logischen Schaltkreises auf eine programmierbare Nachschlagetabelle | [2005/38] | English: | A method for mapping a logic circuit to a programmable look up table | [2004/45] | French: | Procédé de mappage d'un circuit logique dans une table de consultation | [2004/45] |
| Former [2004/45] | Verfahren zur Abbildung eines logischen Schlatkreises auf eine programmierbare Nachschlagetabelle | Examination procedure | 17.03.2006 | Examination requested [2006/20] | 08.06.2007 | Despatch of a communication from the examining division (Time limit: M06) | 14.12.2007 | Reply to a communication from the examining division | 02.02.2010 | Despatch of a communication from the examining division (Time limit: M06) | 02.08.2010 | Reply to a communication from the examining division | 28.06.2012 | Application refused, date of legal effect [2012/49] | 28.06.2012 | Date of oral proceedings | 20.07.2012 | Despatch of communication that the application is refused, reason: substantive examination [2012/49] | 20.07.2012 | Minutes of oral proceedings despatched | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 08.06.2007 | Fees paid | Renewal fee | 28.04.2006 | Renewal fee patent year 03 | 25.04.2007 | Renewal fee patent year 04 | 18.03.2008 | Renewal fee patent year 05 | 07.04.2009 | Renewal fee patent year 06 | 15.03.2010 | Renewal fee patent year 07 | 06.04.2011 | Renewal fee patent year 08 | 19.03.2012 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] - ANDERSON J H ET AL, "Power-aware technology mapping for LUT-based FPGAs", FIELD-PROGRAMMABLE TECHNOLOGY, 2002. (FPT). PROCEEDINGS. 2002 IEEE INTERNATIONAL CONFERENCE ON 16-18 DEC. 2002, PISCATAWAY, NJ, USA,IEEE, (20021216), ISBN 0-7803-7574-2, pages 211 - 218, XP010636529 [X] 1,2 * page 212, column R * * page 213, column R - page 215, column L * * figure 1 * | [X] - CONG J ET AL, "Cut ranking and pruning: enabling a general and efficient FPGA mapping solution", FPGA'99. AGM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS ACM NEW YORK, NY, USA, (1999), ISBN 1-58113-088-0, pages 29 - 35, XP002337810 [X] 1,2 * page 29, column L - page 30, column R * * page 33, column L * DOI: http://dx.doi.org/10.1145/296399.296425 | [A] - CONG J ET AL, "FLOW MAP: AN OPTIMAL TECHNOLOGY MAPPING ALGORITHM FOR DELAY OPTIMIZATION IN LOOKUP-TABLE BASED FPGA DESIGNS", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE INC. NEW YORK, US, (199401), vol. 13, no. 1, ISSN 0278-0070, pages 1 - 12, XP000452162 [A] 1,2 * the whole document * DOI: http://dx.doi.org/10.1109/43.273754 |