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EP1494286
European procedure
Extract from the Register of European Patents
EP About this file: EP1494286
| EP1494286 - Integrated overvoltage and reverse voltage protection circuit that uses field effect transistor with source and drain offset [Right-click to bookmark this link] | |||
| Former [2005/01] | Field effect transistor with source and drain offset, and integrated overvoltage and reverse voltage protection circuit that uses the same | ||
| [2012/28] | Status | No opposition filed within time limit Status updated on 18.10.2013 Database last updated on 11.04.2026 | Most recent event Tooltip | 18.10.2013 | No opposition filed within time limit | published on 20.11.2013 [2013/47] | Applicant(s) | For all designated states Semiconductor Components Industries, LLC 5005 E. McDowell Road Phoenix, AZ 85008 / US | [2012/50] |
| Former [2009/51] | For all designated states Semiconductor Components Industries, LLC 5005 E. McDowell Road Phoenix AZ 85008 / US | ||
| Former [2005/01] | For all designated states AMI Semiconductor, Inc. 2300 Buckskin Road Pocatello, Idaho 83201 / US | Inventor(s) | 01 /
Scott, Greg 4634 North Rapid Creek Road Inkom, Idaho 83245 / US | 02 /
Laraia, J. Marcos 2936 Butte Street Potacello, Idaho 83201 / US | [2005/01] | Representative(s) | Grünecker Patent- und Rechtsanwälte PartG mbB Leopoldstraße 4 80802 München / DE | [N/P] |
| Former [2012/50] | Grünecker, Kinkeldey, Stockmair & Schwanhäusser Leopoldstrasse 4 80802 München / DE | ||
| Former [2005/01] | Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät Maximilianstrasse 58 80538 München / DE | Application number, filing date | 04011784.8 | 18.05.2004 | [2005/01] | Priority number, date | US20030611714 | 01.07.2003 Original published format: US 611714 | [2005/01] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1494286 | Date: | 05.01.2005 | Language: | EN | [2005/01] | Type: | A3 Search report | No.: | EP1494286 | Date: | 01.04.2009 | [2009/14] | Type: | B1 Patent specification | No.: | EP1494286 | Date: | 12.12.2012 | Language: | EN | [2012/50] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 27.02.2009 | Classification | IPC: | H01L27/02 | [2005/01] | CPC: |
H10D89/811 (EP,US)
| Designated contracting states | DE, FR, IT [2009/50] |
| Former [2005/01] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Integrierter Überspannungsschutz und Sperrspannungsschutz mit Feldeffekttransistoren mit Drain- und Source Offset | [2012/29] | English: | Integrated overvoltage and reverse voltage protection circuit that uses field effect transistor with source and drain offset | [2012/28] | French: | Protection intégrée contre les surtensions et les tensions inverses utilisant des transistors à effet de champ avec source et drain décalés | [2012/28] |
| Former [2005/01] | Feldeffekttransistor mit Drain und Source Offset und integriertem Überspannungsschutz und Sperrspannungsschutz mit einem solchen Transistor | ||
| Former [2005/01] | Field effect transistor with source and drain offset, and integrated overvoltage and reverse voltage protection circuit that uses the same | ||
| Former [2005/01] | Transistor à effet de champ avec source et drain décalés et protection intégrée contre les surtensions et les tensions inverses utilisant ledit dispositif | Examination procedure | 28.09.2009 | Examination requested [2009/46] | 02.10.2009 | Loss of particular rights, legal effect: designated state(s) | 21.10.2009 | Despatch of a communication from the examining division (Time limit: M04) | 09.11.2009 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GB, GR, HU, IE, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR | 10.02.2010 | Reply to a communication from the examining division | 23.01.2012 | Despatch of a communication from the examining division (Time limit: M04) | 24.05.2012 | Reply to a communication from the examining division | 02.07.2012 | Communication of intention to grant the patent | 25.10.2012 | Fee for grant paid | 25.10.2012 | Fee for publishing/printing paid | Divisional application(s) | EP11184888.3 / EP2408010 | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 21.10.2009 | Opposition(s) | 13.09.2013 | No opposition filed within time limit [2013/47] | Fees paid | Renewal fee | 27.07.2006 | Renewal fee patent year 03 | 30.05.2007 | Renewal fee patent year 04 | 28.05.2008 | Renewal fee patent year 05 | 07.05.2009 | Renewal fee patent year 06 | 31.03.2010 | Renewal fee patent year 07 | 10.05.2011 | Renewal fee patent year 08 | 19.03.2012 | Renewal fee patent year 09 | Penalty fee | Additional fee for renewal fee | 31.05.2006 | 03 M06 Fee paid on 27.07.2006 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XA] US5047820 (GARNETT MARTIN E et al.) | [XA] EP0295391 (POWER INTEGRATIONS INC et al.) | [XA] US2001019278 (SUDO MINORU et al.) [X] 21-24 * abstract * * column 4, line 62 - column 5, line 5 * * figures 8,9 *[A] 1-20 | [XA] US2002130646 (ZADEH ALI ENAYAT et al.) [X] 21-24 * abstract * * column 6, line 49 - column 7, line 35 * * figure 5 *[A] 1-20 | by applicant | US5047820 | EP0295391 |