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Extract from the Register of European Patents

EP About this file: EP1538533

EP1538533 - Improved FFT/IFFT processor [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  03.11.2017
Database last updated on 14.09.2024
FormerRequest for examination was made
Status updated on  26.07.2017
Most recent event   Tooltip03.11.2017Application deemed to be withdrawnpublished on 06.12.2017  [2017/49]
Applicant(s)For all designated states
STMicroelectronics Pvt. Ltd.
Plot No. 1, Knowledge Park III
201308 Greater Noida, Uttar Pradesh / IN
[2008/01]
Former [2005/23]For:DE  FR  GB  IT 
STMicroelectronics Pvt. Ltd
Plot No. 2 & 3, Sector 16A, Institutional Area
Noida 201 301, Uttar Pradesh / IN
Inventor(s)01 / Saha, Kaushik
A2 Staff Flats, I.P. College Shamnath Marg
Dehli - 110 054 / IN
02 / Maiti, Srijib Narayan
R-5/1, Duk Bungalow Road Saratpalli
Midnapore - 721 101 West Bengal / IN
03 / Cornero, Marco
Via Volta, 43
22100 Como / IT
 [2005/23]
Representative(s)Cerbaro, Elena, et al
Studio Torta S.p.A.
Via Viotti, 9
10121 Torino / IT
[2014/44]
Former [2013/23]Bergadano, Mirko, et al
Studio Torta S.p.A.
Via Viotti, 9
10121 Torino / IT
Former [2008/45]Jorio, Paolo, et al
STUDIO TORTA Via Viotti 9
10121 Torino / IT
Former [2005/23]Jorio, Paolo, et al
STUDIO TORTA S.r.l., Via Viotti, 9
10121 Torino / IT
Application number, filing date04106295.103.12.2004
[2005/23]
Priority number, dateIN2003DEL152005.12.2003         Original published format: IN DE15202003
[2005/23]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1538533
Date:08.06.2005
Language:EN
[2005/23]
Type: A3 Search report 
No.:EP1538533
Date:22.02.2006
[2006/08]
Search report(s)(Supplementary) European search report - dispatched on:EP09.01.2006
ClassificationIPC:G06F17/14
[2005/23]
CPC:
G06F17/142 (EP,US)
Designated contracting statesDE,   FR,   GB,   IT [2006/43]
Former [2005/23]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  MC,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:Verbesserter FFT/IFFT-Prozessor[2005/23]
English:Improved FFT/IFFT processor[2005/23]
French:Processeur FFT/IFFT amélioré[2005/23]
Examination procedure18.08.2006Examination requested  [2006/40]
01.07.2017Application deemed to be withdrawn, date of legal effect  [2017/49]
27.07.2017Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time  [2017/49]
Fees paidRenewal fee
27.12.2006Renewal fee patent year 03
27.12.2007Renewal fee patent year 04
27.03.2008Renewal fee patent year 05
30.12.2009Renewal fee patent year 06
24.12.2010Renewal fee patent year 07
27.12.2011Renewal fee patent year 08
26.12.2012Renewal fee patent year 09
25.12.2013Renewal fee patent year 10
05.01.2015Renewal fee patent year 11
04.01.2016Renewal fee patent year 12
Penalty fee
Additional fee for renewal fee
31.12.201613   M06   Not yet paid
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]WO0169424  (JABER ASSOCIATES L L C [US], et al) [A] 1-8 * page 6, line 14 - page 7, line 20 * * page 16, line 19 - page 17, line 2; figure 10 *;
 [PX]EP1447752  (ST MICROELECTRONICS PVT LTD [IN]) [PX] 1-8 * the whole document *;
 [X]  - CHU E ET AL, Inside the FFT Black Box: Serial and Parallel Fast Fourier Transform Algorithms, CRC PRESS LLC, (2000), XP002360703 [X] 1-8 * chapter 8 (page 69 - page 79) * * chapter 17 (page 177 - page 182) * * sections 19.2.3, 19.2.4, 19.3 (page 209 - page 210) * * section 21.1.3 (page 226) *
 [DX]  - PIEDRA R M, Parallel 1-D FFT Implementation With TMS320C4x DSPs, TEXAS INSTRUMENTS, APPLICATION REPORT SPRA108, (199402), XP002360704 [DX] 1-8 * section "Parallel DIT FFT" (page 7 - page 11) * * section "B) Decimation-in-Time (DIT) FFT" (page 16 - page 17) *
 [A]  - DAWOUD D S, "An effective memory addressing scheme for multiprocessor FFT system", 2002 6TH. IEEE AFRICON CONFERENCE. UNIVERSITY OF PRETORIA, GEORGE, SOUTH AFRICA, 2-4 OCTOBER 2002, IEEE, NEW YORK, NY, US, (20021002), vol. 1, ISBN 0-7803-7570-X, pages 29 - 34, XP010621641 [A] 1-8 * section 3 *

DOI:   http://dx.doi.org/10.1109/AFRCON.2002.1146801
 [A]  - DAWOUD D S, "New hardware implementation of parallel 1D FFT", 2002 6TH. IEEE AFRICON CONFERENCE. UNIVERSITY OF PRETORIA, GEORGE, SOUTH AFRICA, 2-4 OCTOBER 2002, IEEE, NEW YORK, NY, US, (20021002), vol. 1, ISBN 0-7803-7570-X, pages 35 - 40, XP010621642 [A] 1-8 * section 3 *

DOI:   http://dx.doi.org/10.1109/AFRCON.2002.1146802
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.