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Extract from the Register of European Patents

EP About this file: EP1593014

EP1593014 - DIGITAL SIGNAL PROCESSOR ARCHITECTURE OPTIMIZED FOR CONTROLLING SWITCHED MODE POWER SUPPLY [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  30.03.2012
Database last updated on 13.07.2024
Most recent event   Tooltip18.07.2014Lapse of the patent in a contracting state
New state(s): HU		published on 20.08.2014  [2014/34]
Applicant(s)For all designated states
Power-One, Inc.
740 Calle Plano
Camarillo, California 93012 / US
[2011/21]
Former [2006/09]For all designated states
Power-One, Inc.
740 Calle Plano Camarillo
California 93012 / US
Former [2005/45]For all designated states
Power-One Limited
Corporate Centre, West Bay Road, P.O. Box 31106 SMB British West Indies
Grand Cayman / KY
Inventor(s)01 / CHAPUIS, Alain
Riedikerstrasse 86A
8616 Riedikon / CH
 [2006/45]
Former [2005/45]01 / CHAPUIS, Alain
3451 Oak Lane
Morgan Hill, California 95037 / US
Representative(s)Winter, Brandl - Partnerschaft mbB
Alois-Steinecker-Straße 22
85354 Freising / DE
[N/P]
Former [2005/45]Winter, Brandl, Fürniss, Hübner Röss, Kaiser, Polte Partnerschaft Patent- und Rechtsanwaltskanzlei
Alois-Steinecker-Strasse 22
85354 Freising / DE
Application number, filing date04708196.304.02.2004
[2005/45]
WO2004US03174
Priority number, dateUS2003036145210.02.2003         Original published format: US 361452
[2005/45]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report
No.:WO2004073149
Date:26.08.2004
Language:EN
[2004/35]
Type: A2 Application without search report 
No.:EP1593014
Date:09.11.2005
Language:EN
The application published by WIPO in one of the EPO official languages on 26.08.2004 takes the place of the publication of the European patent application.
[2005/45]
Type: B1 Patent specification 
No.:EP1593014
Date:25.05.2011
Language:EN
[2011/21]
Search report(s)International search report - published on:US24.02.2005
(Supplementary) European search report - dispatched on:EP27.03.2007
ClassificationIPC:H02M3/157
[2007/17]
CPC:
H02M3/157 (EP,KR,US)
Former IPC [2005/45]G05F1/40
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   RO,   SE,   SI,   SK,   TR [2005/45]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
TitleGerman:ZUR STEUERUNG EINES SCHALTNETZTEILS OPTIMIERTE DIGITALSIGNALPROZESSORARCHITEKTUR[2011/30]
English:DIGITAL SIGNAL PROCESSOR ARCHITECTURE OPTIMIZED FOR CONTROLLING SWITCHED MODE POWER SUPPLY[2005/45]
French:ARCHITECTURE DE PROCESSEUR A SIGNAUX DIGITAUX OPTIMISE POUR COMMANDER UNE ALIMENTATION EN MODE COMMUTE[2005/45]
Former [2005/45]ZUR STEUERUNG EINES SCHALTNETZTEILOPTIMIERTE DIGITALSIGNALPROZESSORARCHITEKTUR
Entry into regional phase16.06.2005National basic fee paid 
16.06.2005Search fee paid 
16.06.2005Designation fee(s) paid 
16.06.2005Examination fee paid 
Examination procedure13.08.2004Request for preliminary examination filed
International Preliminary Examining Authority: US
16.06.2005Examination requested  [2005/45]
14.10.2008Despatch of a communication from the examining division (Time limit: M06)
24.04.2009Reply to a communication from the examining division
10.12.2010Communication of intention to grant the patent
13.04.2011Fee for grant paid
13.04.2011Fee for publishing/printing paid
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  14.10.2008
Opposition(s)28.02.2012No opposition filed within time limit [2012/18]
Fees paidRenewal fee
06.02.2006Renewal fee patent year 03
05.02.2007Renewal fee patent year 04
08.02.2008Renewal fee patent year 05
09.02.2009Renewal fee patent year 06
08.02.2010Renewal fee patent year 07
08.02.2011Renewal fee patent year 08
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU04.02.2004
AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
IT25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
TR25.05.2011
BG25.08.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
IE04.02.2012
LU04.02.2012
[2014/34]
Former [2014/27]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
IT25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
TR25.05.2011
BG25.08.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
IE04.02.2012
LU04.02.2012
Former [2014/21]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
IT25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
TR25.05.2011
BG25.08.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
IE04.02.2012
Former [2013/29]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
IT25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
BG25.08.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
IE04.02.2012
Former [2013/08]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
IT25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
IE04.02.2012
Former [2012/23]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
IT25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2012/10]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
DK25.05.2011
EE25.05.2011
FI25.05.2011
NL25.05.2011
RO25.05.2011
SE25.05.2011
SI25.05.2011
SK25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2012/09]AT25.05.2011
BE25.05.2011
CY25.05.2011
CZ25.05.2011
EE25.05.2011
FI25.05.2011
NL25.05.2011
SE25.05.2011
SI25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2012/01]AT25.05.2011
BE25.05.2011
CY25.05.2011
FI25.05.2011
NL25.05.2011
SE25.05.2011
SI25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2011/52]AT25.05.2011
CY25.05.2011
FI25.05.2011
SE25.05.2011
SI25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2011/50]CY25.05.2011
FI25.05.2011
SE25.05.2011
SI25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2011/49]CY25.05.2011
FI25.05.2011
SE25.05.2011
GR26.08.2011
ES05.09.2011
PT26.09.2011
Former [2011/47]PT26.09.2011
Documents cited:Search[A]US4761725  (HENZE CHRISTOPHER P [US]) [A] 1,14* column 5, lines 29-31; figures 1,3 *;
 [A]US6194883  (SHIMAMORI HIROSHI [JP]) [A] 1,14 * the whole document *;
 [A]  - PATELLA B J ET AL, "High-frequency digital controller IC for DC/DC converters", APEC 2002. 17TH. ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION. DALLAS, TX, MARCH 10 - 14, 2002, ANNUAL APPLIED POWER ELECTRONICS CONFERENCE, NEW YORK, NY : IEEE, US, (20020310), VOL. 2 OF 2. CONF. 17, ISBN 0-7803-7404-5, pages 374 - 380, XP010582947 [A] 1,14 * page 375, column R; figure 3 *

DOI:   http://dx.doi.org/10.1109/APEC.2002.989273
International search[Y]US5349523  (INOU KIYOHARU [JP], et al);
 [X]US6194883  (SHIMAMORI HIROSHI [JP])
by applicantUS4761725
 US6194883
    - PATELLA B. J. ET AL., "High-frequency digital controller IC for DC/DC converters", APEC 2002, 17TH. ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, (20020310), vol. 2, pages 374 - 380
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.