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Extract from the Register of European Patents

EP About this file: EP1654770

EP1654770 - METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED REGIONS [Right-click to bookmark this link]
Former [2006/19]STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS
[2010/40]
StatusNo opposition filed within time limit
Status updated on  03.02.2012
Database last updated on 07.10.2024
Most recent event   Tooltip04.10.2013Lapse of the patent in a contracting state
New state(s): HU		published on 06.11.2013  [2013/45]
Applicant(s)For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, NY 10504 / US
[2011/13]
Former [2006/19]For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, N.Y. 10504 / US
Inventor(s)01 / CHEN, Huajie, c/o IBM United Kingdom Limited
Intellectual Property Law, Hursley Park
Winchester, Hampshire SO21 2JN / GB
02 / CHIDAMBARRAO, Dureseti
29 Old Mill Road
Weston, CT 06883 / US
03 / GLUSCHENKOV, Oleg G.
160 Academy Street, Apt. 9H
Poughkeepsie, NY 12601 / US
04 / STEEGEN, An, L., c/o IBM United Kingdom Ltd.
Intellectual Property Law, Hursley Park
Winchester, Hampshire SO21 2JN / GB
05 / YANG, Haining, S.
36 Robinson Lane
Wappingers Falls, NY 12590 / US
 [2007/21]
Former [2006/19]01 / CHEN, Huajie
622 Avalon Lake Road
Danbury, CT 06810 / US
02 / CHIDAMBARRAO, Dureseti
29 Old Mill Road
Weston, CT 06883 / US
03 / GLUSCHENKOV, Oleg G.
160 Academy Street, Apt. 9H
Poughkeepsie, NY 12601 / US
04 / STEEGEN, An, L.
150 Southfield Avenue, Apt. 2483
Stamford, CT 06902 / US
05 / YANG, Haining, S.
36 Robinson Lane
Wappingers Falls, NY 12590 / US
Representative(s)Litherland, David Peter
IBM United Kingdom Limited
Intellectual Property Department
Hursley Park
Winchester, Hampshire SO21 2JN / GB
[N/P]
Former [2006/19]Litherland, David Peter
IBM United Kingdom Limited Intellectual Property Department Hursley Park Winchester
Hampshire SO21 2JN / GB
Application number, filing date04780054.504.08.2004
[2006/19]
WO2004US25152
Priority number, dateUS2003060460704.08.2003         Original published format: US 604607
[2006/19]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report
No.:WO2005017964
Date:24.02.2005
Language:EN
[2005/08]
Type: A2 Application without search report 
No.:EP1654770
Date:10.05.2006
Language:EN
The application published by WIPO in one of the EPO official languages on 24.02.2005 takes the place of the publication of the European patent application.
[2006/19]
Type: B1 Patent specification 
No.:EP1654770
Date:30.03.2011
Language:EN
[2011/13]
Search report(s)International search report - published on:US02.06.2005
(Supplementary) European search report - dispatched on:EP16.06.2008
ClassificationIPC:H01L21/336, H01L21/8238, H01L21/20
[2010/40]
CPC:
H01L21/84 (EP,US); H01L21/8238 (KR); H01L21/823807 (EP,US);
H01L21/823814 (EP,US); H01L27/0922 (EP,US); H01L27/1203 (EP,US);
H01L29/66628 (EP,US); H01L29/66636 (EP,US); H01L29/7848 (EP,US);
H01L21/02532 (EP,US); H01L21/02636 (EP,US); H01L29/165 (EP,US);
H01L29/6656 (EP,US) (-)
Former IPC [2006/19]H01L31/0328, H01L31/0336, H01L21/336, H01L21/8238
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IT,   LI,   LU,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2006/19]
Extension statesALNot yet paid
HRNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
TitleGerman:VERFAHREN ZUR HERSTELLUNG VON CMOS-TRANSISTOREN MIT VERSPANNTEM HALBLEITER MIT GITTERFEHLANGEPASSTEN REGIONEN[2010/40]
English:METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED REGIONS[2010/40]
French:PROCEDE DE FABRICATION DE TRANSISTORS CMOS A SEMI-CONDUCTEURS CONTRAINTS COMPRENANT DES REGIONS A DESACCORD DE RESEAU[2010/40]
Former [2006/19]STRUKTUR UND VERFAHREN ZUR HERSTELLUNG VON CMOS-TRANSISTOREN MIT VERSPANNTEM HALBLEITER MIT GITTERFEHLANGEPASSTER SOURCE- UND DRAIN-REGION
Former [2006/19]STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS
Former [2006/19]STRUCTURE ET PROCEDE DE FABRICATION DE TRANSISTORS CMOS CONTRAINTS A SEMI-CONDUCTEURS COMPRENANT DES REGIONS SOURCE ET DRAIN A DEFAUT D'APPARIEMENT
Entry into regional phase21.02.2006National basic fee paid 
21.02.2006Search fee paid 
21.02.2006Designation fee(s) paid 
21.02.2006Examination fee paid 
Examination procedure03.03.2005Request for preliminary examination filed
International Preliminary Examining Authority: US
21.02.2006Amendment by applicant (claims and/or description)
21.02.2006Examination requested  [2006/19]
01.09.2008Despatch of a communication from the examining division (Time limit: M04)
08.01.2009Reply to a communication from the examining division
23.04.2010Despatch of a communication from the examining division (Time limit: M04)
20.08.2010Reply to a communication from the examining division
23.11.2010Communication of intention to grant the patent
15.02.2011Fee for grant paid
15.02.2011Fee for publishing/printing paid
Opposition(s)02.01.2012No opposition filed within time limit [2012/10]
Fees paidRenewal fee
11.08.2006Renewal fee patent year 03
15.08.2007Renewal fee patent year 04
18.08.2008Renewal fee patent year 05
26.08.2009Renewal fee patent year 06
19.08.2010Renewal fee patent year 07
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
HU30.03.2011
IT30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
TR30.03.2011
BG30.06.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
LU04.08.2011
MC31.08.2011
[2013/45]
Former [2013/44]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
IT30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
TR30.03.2011
BG30.06.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
LU04.08.2011
MC31.08.2011
Former [2013/29]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
IT30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
BG30.06.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
LU04.08.2011
MC31.08.2011
Former [2013/25]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
IT30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
LU04.08.2011
MC31.08.2011
Former [2012/23]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
IT30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
MC31.08.2011
Former [2012/18]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
MC31.08.2011
Former [2012/11]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
PL30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
Former [2012/10]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
DK30.03.2011
EE30.03.2011
FI30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
Former [2011/50]AT30.03.2011
BE30.03.2011
CY30.03.2011
CZ30.03.2011
EE30.03.2011
FI30.03.2011
RO30.03.2011
SI30.03.2011
SK30.03.2011
GR01.07.2011
ES11.07.2011
PT01.08.2011
PL22.08.2011
Former [2011/47]AT30.03.2011
BE30.03.2011
CY30.03.2011
EE30.03.2011
FI30.03.2011
SI30.03.2011
GR01.07.2011
PT01.08.2011
Former [2011/41]AT30.03.2011
BE30.03.2011
CY30.03.2011
FI30.03.2011
SI30.03.2011
GR01.07.2011
Former [2011/40]AT30.03.2011
CY30.03.2011
FI30.03.2011
SI30.03.2011
GR01.07.2011
Former [2011/36]GR01.07.2011
Documents cited:Search[X]US6165826  (CHAU ROBERT S [US], et al) [X] 1,2,5,6,8-13 * column 6, line 1 - line 4; figure 3 * * column 8, line 31 - line 64 * * column 12, line 16 - line 20 *;
 [A]US2002063292  (ARMSTRONG MARK [US], et al) [A] 1,12,13* paragraphs [0005] - [0007]; figure 2 *;
 [Y]US6495402  (YU BIN [US], et al) [Y] 3,4,14-20 * column 3, line 14 - line 16; figure 3 * * column 4, lines 24-37 *;
 [Y]US2003027414  (KO YOUNG-GUN [KR]) [Y] 21-25 * paragraphs [0011] , [0012]; figures 6-15 *;
 [XY]US2003080361  (MURTHY ANAND [US], et al) [X] 1-3,5-13 * paragraphs [0015] , [0029]; figures 1-6 * [Y] 1-12,21-25;
 [Y]US2003111699  (WASSHUBER CHRISTOPH [US], et al) [Y] 1-12 * paragraphs [0004] , [0030] , [0031]; figures 3-6 *;
 [E]US2004173815  (YEO YEE-CHIA [SG], et al) [E] 1-6,8-12 * paragraphs [0030] - [0034]; figures 3A,3B *;
 [E]WO2005010982  (INTEL CORP [US]) [E] 1,2,5,6,8-12 * paragraphs [0024] , [0025] , [0028] , [0036] , [0037]; figures 1-8 *;
 [XY]  - GANNAVARAM S ET AL, "LOW TEMPERATURE ( 800öC) RECESSED JUNCTION SELECTIVE SILICON-GERMANIUM SOURCE/DRAIN TECHNOLOGY FOR SUB-70 NM CMOS", INTERNATIONAL ELECTRON DEVICES MEETING 2000. IEDM. TECHNICAL DIGEST. SAN FRANCISCO, CA, DEC. 10 - 13, 2000; [INTERNATIONAL ELECTRON DEVICES MEETING], NEW YORK, NY : IEEE, US, (20001210), ISBN 978-0-7803-6439-4, pages 437 - 440, XP000988876 [X] 1,2,5,6,8,9,13 * page 437; figures 1,3,18,19 * * page 438, column R, paragraph 1 * [Y] 3,4,14-20
International search[A]US5155571  (WANG KANG L [US], et al);
 [A]US2001003364  (SUGAWARA MINORU [JP], et al)
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.