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Extract from the Register of European Patents

EP About this file: EP1603026

EP1603026 - Disk array device and battery output control method for disk array device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  13.11.2008
Database last updated on 16.09.2024
Most recent event   Tooltip13.11.2008No opposition filed within time limitpublished on 10.12.2008  [2008/50]
Applicant(s)For all designated states
Hitachi, Ltd.
6, Kanda Surugadai 4-chome
Chiyoda-ku
Tokyo 100-8220 / JP
[N/P]
Former [2008/01]For all designated states
Hitachi, Ltd.
6, Kanda Surugadai 4-chome Chiyoda-ku
Tokyo 100-8220 / JP
Former [2005/49]For all designated states
Hitachi, Ltd.
6, Kanda Surugadai 4-chome Chiyoda-ku
Tokyo 100-8220 / JP
Inventor(s)01 / Hayashi, Katsunori, Hitachi, Ltd.
IP Group, Marunoucho Bldg., 12F, 1-6-14 Marunouchi
Chiyoda-ku, Tokyo 100-8220 / JP
 [2005/49]
Representative(s)Holt, Daniel Richard, et al
Mewburn Ellis LLP
33 Gutter Lane
London
EC2V 8AS / GB
[N/P]
Former [2005/49]Holt, Daniel Richard, et al
Mewburn Ellis LLP York House 23 Kingsway
London WC2B 6HP / GB
Application number, filing date05252535.922.04.2005
[2005/49]
Priority number, dateJP2004016400702.06.2004         Original published format: JP 2004164007
[2005/49]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1603026
Date:07.12.2005
Language:EN
[2005/49]
Type: A3 Search report 
No.:EP1603026
Date:22.03.2006
[2006/12]
Type: B1 Patent specification 
No.:EP1603026
Date:02.01.2008
Language:EN
[2008/01]
Search report(s)(Supplementary) European search report - dispatched on:EP03.02.2006
ClassificationIPC:G06F3/06, G06F1/00, G06F1/26, G06F1/30, G06F1/32, G11B33/12, H02J1/10
[2006/12]
CPC:
G06F11/1441 (EP,US); G06F1/263 (EP,US); G06F1/305 (EP,US);
G06F1/3221 (EP,US); G11B33/126 (EP,US); G06F3/0601 (EP,US);
G06F3/0673 (EP,US); Y02D10/00 (EP,US) (-)
Former IPC [2005/49]G06F3/06, G06F1/00
Designated contracting statesDE,   FR,   GB [2006/48]
Former [2005/49]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  MC,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:Speicherplattenanordnung und Verfahren zur Steuerung eines Batterieausgangs für Speicherplattenanordnung[2005/49]
English:Disk array device and battery output control method for disk array device[2005/49]
French:Dispositif de réseau de disques et procédé de gestion de sortie de batterie pour dispositif de réseau de disques[2005/49]
Examination procedure11.05.2005Examination requested  [2005/49]
22.05.2006Despatch of a communication from the examining division (Time limit: M04)
27.09.2006Reply to a communication from the examining division
07.02.2007Despatch of a communication from the examining division (Time limit: M02)
23.02.2007Reply to a communication from the examining division
22.06.2007Communication of intention to grant the patent
01.11.2007Fee for grant paid
01.11.2007Fee for publishing/printing paid
Opposition(s)03.10.2008No opposition filed within time limit [2008/50]
Fees paidRenewal fee
24.04.2007Renewal fee patent year 03
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[Y]US5675816  (HIYOSHI YUTAKA [JP], et al) [Y] 1-20 * column 11, lines 27-47 * * column 12, lines 4-21 * * column 13, lines 19-50 * * column 14, lines 8-17 * * column 14, lines 45-54 * * figures 1,4A,5A *;
 [A]US2001046118  (YAMANASHI AKIRA [JP], et al) [A] 1,16 * paragraphs [0047] , [0053] * * figure 3 *;
 [A]US2003085622  (HAILEY JEFFREY C [US]) [A] 1,16 * paragraphs [0029] - [0031] * * figures 4,5 *;
 [Y]EP1320167  (MAGNETEK SPA [IT]) [Y] 1-20 * paragraph [0012] * * figure 2 *;
 [A]EP1361516  (HITACHI LTD [JP]) [A] 1,16 * paragraphs [0016] - [0020] *;
 [A]US2004068670  (SUZUKI HIROSHI [JP], et al) [A] 1,16 * paragraphs [0022] , [0053] * * figure 1 *;
 [A]  - BENINI L ET AL, "Discharge current steering for battery lifetime optimization", LOW POWER ELECTRONICS AND DESIGN, 2002. ISLPED '02. PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON AUG. 12-14, 2002, PISCATAWAY, NJ, USA,IEEE, (20020812), ISBN 1-58113-475-4, pages 118 - 123, XP010600865 [A] 1,16 * page 118, column R, paragraph 3 * * page 118, column R, paragraph 4 - page 119, column L, paragraph 1 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.