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EP1670057
European procedure
Extract from the Register of European Patents
EP About this file: EP1670057
| EP1670057 - Manufacturing method of chip integrated substrate [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 31.12.2010 Database last updated on 02.11.2024 | Most recent event Tooltip | 31.12.2010 | No opposition filed within time limit | published on 02.02.2011 [2011/05] | Applicant(s) | For all designated states SHINKO ELECTRIC INDUSTRIES CO., LTD. 80 Oshimada-machi Nagano-shi, Nagano 381-2287 / JP | [2006/24] | Inventor(s) | 01 /
Machida, Yoshihiro, c/o Shinko Elec. Ind. Co. Ltd. 80, Oshimadamachi Nagano-shi, Nagano 381-2287 / JP | 02 /
Yamano, Takaharu, c/o Shinko Elec. Ind. Co. Ltd. 80, Oshimadamachi Nagano-shi, Nagano 381-2287 / JP | [2006/24] | Representative(s) | Vinsome, Rex Martin, et al Urquhart-Dykes & Lord LLP 12th Floor Cale Cross House 156 Pilgrim Street Newcastle-upon-Tyne NE1 6SU / GB | [N/P] |
| Former [2009/49] | Vinsome, Rex Martin, et al Urquhart-Dykes & Lord LLP Cale Cross House Pilgrim Street 156 Newcastle upon Tyne NE1 6SU / GB | ||
| Former [2007/50] | Vinsome, Rex Martin, et al Urquhart-Dykes & Lord LLP 12th Floor Cale Cross House 156 Pilgrim Street Newcastle-upon-Tyne NE1 6SU / GB | ||
| Former [2006/24] | Rees, Alexander Ellison, et al Urquhart-Dykes & Lord LLP 30 Welbeck Street London W1G 8ER / GB | Application number, filing date | 05256610.6 | 25.10.2005 | [2006/24] | Priority number, date | JP20040354172 | 07.12.2004 Original published format: JP 2004354172 | [2006/24] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1670057 | Date: | 14.06.2006 | Language: | EN | [2006/24] | Type: | B1 Patent specification | No.: | EP1670057 | Date: | 24.02.2010 | Language: | EN | [2010/08] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.04.2006 | Classification | IPC: | H01L23/538, H01L21/56, // H01L21/60 | [2009/44] | CPC: |
H01L23/5389 (EP,US);
H01L21/28 (KR);
H01L24/24 (EP,US);
H01L24/82 (EP,US);
H01L2224/2402 (EP,US);
H01L2224/24226 (EP,US);
H01L2924/01004 (EP,US);
H01L2924/01006 (EP,US);
H01L2924/01013 (EP,US);
H01L2924/01019 (EP,US);
H01L2924/01029 (EP,US);
H01L2924/0103 (EP,US);
H01L2924/01033 (EP,US);
H01L2924/01078 (EP,US);
H01L2924/01079 (EP,US);
| C-Set: |
H01L2924/12042, H01L2924/00 (EP,US)
|
| Former IPC [2006/24] | H01L23/538, H01L21/56 | Designated contracting states | DE [2007/08] |
| Former [2006/24] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Herstellungsverfahren eines integrierten Chip-Substrat | [2006/24] | English: | Manufacturing method of chip integrated substrate | [2006/24] | French: | Procédé de fabrication d'un substrat comportant une puce | [2006/24] | Examination procedure | 25.09.2006 | Amendment by applicant (claims and/or description) | 26.09.2006 | Examination requested [2006/45] | 06.11.2009 | Communication of intention to grant the patent | 12.01.2010 | Fee for grant paid | 12.01.2010 | Fee for publishing/printing paid | Opposition(s) | 25.11.2010 | No opposition filed within time limit [2011/05] | Fees paid | Renewal fee | 25.09.2007 | Renewal fee patent year 03 | 07.10.2008 | Renewal fee patent year 04 | 13.10.2009 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP1304742 (MATSUSHITA ELECTRIC IND CO LTD [JP]) [X] 1,2,9,11,12 * paragraphs [0001] , [0002] * * paragraphs [0039] - [0046]; figure 1 * * paragraphs [0047] - [0054]; figures 2A-2D * * paragraph [0055]; figure 3 *; | [X]US2003085058 (KOMATSU SHINGO [JP], et al) [X] 1-4,9,11,12 * paragraphs [0001] - [0007] * * paragraphs [0156] - [0163]; figures 4(a)-4(j) *; | [X]US2003227077 (TOWLE STEVEN [US], et al) [X] 1,3-6,8-12 * paragraphs [0005] - [0009] * * paragraphs [0023] - [0025]; figures 1-8 * * paragraphs [0026] - [0033]; figures 9-19 * * paragraph [0037]; figure 20 * * paragraph [0046]; figure 33 *; | [X]US2004195691 (MORIYASU AKIYOSHI [JP], et al) [X] 1,2,4,8,9,11,12 * paragraphs [0016] - [0020] * * paragraphs [0031] - [0037]; figures 1(a),1(b) * * paragraphs [0052] - [0056]; figures 3(a-3(e)) ** paragraphs [0064] , [0065] * | by applicant | JP2004165277 | JP2004354172 |