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EP1717864
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EP About this file: EP1717864
| EP1717864 - Method for managing the stress configuration in the channel of a MOS transistor, and corresponding integrated circuit. [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 21.12.2007 Database last updated on 09.09.2024 | Most recent event Tooltip | 10.10.2008 | Change - representative | published on 12.11.2008 [2008/46] | Applicant(s) | For all designated states STMicroelectronics (Crolles 2) SAS 850, rue Jean Monnet 38926 Crolles / FR | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
| Former [2006/44] | For all designated states STMicroelectronics (Crolles 2) SAS 850, rue Jean Monnet 38926 Crolles / FR | ||
| For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | Inventor(s) | 01 /
Fiori, Vincent Parc du Roy, 8, rue de Moucherotte 301B 38360 Sassenage / FR | 02 /
Orain, Stéphane 38, chemin de la Taillat 38240 Meylan / FR | 03 /
Ortolland, Claude 33 Le Pré Dex 73230 Farby / FR | [2006/44] | Representative(s) | Zapalowicz, Francis Casalonga & Partners Bayerstrasse 71/73 80335 München / DE | [N/P] |
| Former [2008/46] | Zapalowicz, Francis Bureau Casalonga & Josse Bayerstrasse 71/73 80335 München / DE | ||
| Former [2006/44] | Zapalowicz, Francis Bureau Casalonga & Josse Bayerstrasse 71/73 80335 München / DE | Application number, filing date | 05290922.3 | 27.04.2005 | [2006/44] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1717864 | Date: | 02.11.2006 | Language: | EN | [2006/44] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 26.05.2006 | Classification | IPC: | H01L29/78, H01L21/8238, H01L27/092 | [2006/44] | CPC: |
H01L21/76829 (EP);
H01L21/76825 (EP);
H01L29/7842 (EP);
H01L21/823807 (EP);
H01L29/7833 (EP)
| Designated contracting states | (deleted) [2007/28] |
| Former [2006/44] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Verfahren zur Verwaltung von Stressanordnung im Kanal eines MOS-Transistors und entsprechende integrierte Schaltung | [2006/44] | English: | Method for managing the stress configuration in the channel of a MOS transistor, and corresponding integrated circuit. | [2006/44] | French: | Méthode pour gérer la configuration du stress dans le canal d'un transistor MOS et circuit intégré correspondant | [2006/44] | Examination procedure | 03.05.2007 | Application deemed to be withdrawn, date of legal effect [2008/04] | 28.08.2007 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2008/04] | Fees paid | Penalty fee | Penalty fee Rule 85a EPC 1973 | 11.06.2007 | DE M01 Not yet paid | 11.06.2007 | FR M01 Not yet paid | 11.06.2007 | GB M01 Not yet paid | 11.06.2007 | IT M01 Not yet paid | Penalty fee Rule 85b EPC 1973 | 11.06.2007 | M01 Not yet paid | Additional fee for renewal fee | 30.04.2007 | 03 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US5641545 (SANDHU GURTEJ S [US]) [X] 12,14 * figure 3 *; | [X]US2002076947 (LI WEIMIN [US], et al) [X] 12,14 * figure 5 *; | [X]US2004135234 (MORIN PIERRE [FR], et al) [X] 1,2,9,11-13,18,19 * paragraphs [0006] - [0037] *; | [X]US2004251479 (TSUTSUI MASAFUMI [JP], et al) [X] 1,3-6,9-12,18,19 * paragraphs [0024] - [0069]; figures 1-5 *; | [X]US2005019998 (HUANG CHIEN-CHAO [TW], et al) [X] 1-3,12-14 * paragraph [0004] *; | [E]US2005093030 (DORIS BRUCE B [US], et al) [E] 1,4-6,12,18,19 * paragraphs [0028] - [0032] *; | [E]US2005136606 (RULKE HARTMUT [DE], et al) [E] 1,3-6,12-14* figures 1,3 *; | [E]US2005158955 (YANG HAINING S [US], et al) [E] 1,3,12,14 * figure 8 *; | [X] - ARGHAVANI R ET AL, "STRESS MANAGEMENT IN SUB-90-NM TRANSISTOR ARCHITECTURE", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, (200410), vol. 51, no. 10, ISSN 0018-9383, pages 1740 - 1743, XP001211152 [X] 1 * page 1743 * DOI: http://dx.doi.org/10.1109/TED.2004.835993 | [X] - GOTO K ET AL, "Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs", ELECTRON DEVICES MEETING, 2004. IEDM TECHNICAL DIGEST. IEEE INTERNATIONAL SAN FRANCISCO, CA, USA DEC. 13-15, 2004, PISCATAWAY, NJ, USA,IEEE, (20041213), ISBN 0-7803-8684-1, pages 209 - 212, XP010788740 [X] 1,9,11,14,18,19 * the whole document * DOI: http://dx.doi.org/10.1109/IEDM.2004.1419111 |