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EP1560033
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EP About this file: EP1560033
| EP1560033 - Integrated circuit comprising a secure test mode by resetting of said test mode [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 05.07.2013 Database last updated on 11.09.2024 | Most recent event Tooltip | 05.07.2013 | Application deemed to be withdrawn | published on 07.08.2013 [2013/32] | Applicant(s) | For all designated states STMicroelectronics S.A. 29, Boulevard Romain Rolland 92120 Montrouge / FR | [2005/31] | Inventor(s) | 01 /
Bancel, Frédéric, Cabinet Ballot Novograaf Technologies, 9, rue Claude Chappe, Metz Technopôle, 57070 Metz / FR | 02 /
Hely, David, Cabinet Ballot Novograaf Technologies, 9, rue Claude Chappe, Metz Technopôle, 57070 Metz / FR | [2005/31] | Representative(s) | Brungard, Yves Francois Novagraaf Technologies 11, rue Graham Bell 57070 Metz / FR | [N/P] |
| Former [2009/44] | Brungard, Yves Francois Novagraaf Technologies 11 rue Graham Bell 57070 Metz / FR | ||
| Former [2005/31] | Brungard, Yves Cabinet Ballot - Novagraaf Technologies, 9, rue Claude Chappe, Metz - Technopôle 57070 Metz / FR | Application number, filing date | 05366001.5 | 21.01.2005 | [2005/31] | Priority number, date | FR20040000835 | 29.01.2004 Original published format: FR 0400835 | [2005/31] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP1560033 | Date: | 03.08.2005 | Language: | FR | [2005/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.05.2005 | Classification | IPC: | G01R31/3185, G06F12/14, G01R31/317, G06F21/00 | [2009/49] | CPC: |
G06F21/75 (EP,US);
G01R31/31719 (EP,US);
G01R31/318533 (EP,US)
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| Former IPC [2005/31] | G01R31/3185, G06F12/14, G01R31/317 | Designated contracting states | DE, FR, GB, IT [2006/17] |
| Former [2005/31] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Integrierte Schaltung mit sicherem Testmodus mittels Initialisierung des Testmodus | [2005/31] | English: | Integrated circuit comprising a secure test mode by resetting of said test mode | [2005/31] | French: | Circuit intégré comportant un mode de test sécurisé par initialisation du dit mode de test | [2005/31] | Examination procedure | 26.01.2006 | Examination requested [2006/13] | 14.03.2006 | Despatch of a communication from the examining division (Time limit: M04) | 12.07.2006 | Reply to a communication from the examining division | 05.11.2007 | Despatch of a communication from the examining division (Time limit: M06) | 14.05.2008 | Reply to a communication from the examining division | 08.12.2009 | Despatch of communication that the application is refused, reason: substantive examination {1} | 01.08.2012 | Application deemed to be withdrawn, date of legal effect [2013/32] | 21.11.2012 | Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time [2013/32] | Appeal following examination | 26.01.2010 | Appeal received No. T1462/10 | 08.04.2010 | Statement of grounds filed | 17.05.2013 | Result of appeal procedure: the application was deemed to be withdrawn | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 14.03.2006 | Fees paid | Renewal fee | 29.01.2007 | Renewal fee patent year 03 | 30.01.2008 | Renewal fee patent year 04 | 28.01.2009 | Renewal fee patent year 05 | 28.01.2010 | Renewal fee patent year 06 | 31.01.2011 | Renewal fee patent year 07 | Penalty fee | Additional fee for renewal fee | 31.01.2012 | 08 M06 Not yet paid | 31.01.2013 | 09 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP1089083 (SONY CORP [JP]) [A] 1 * paragraph [0026] - paragraph [0035]; figures 4,5 *; | [A]US2002133773 (RICHTER MICHAEL [DE], et al) [A] 1 * paragraph [0026] - paragraph [0029]; figures 1,2 *; | [X]US2003204801 (TKACIK THOMAS [US], et al) [X] 1-4 * paragraph [0012] - paragraph [0034]; figures 1,2 *; | [A] - JARAMILLO K ET AL, "10 TIPS FOR SUCCESSFUL SCAN DESIGN: PART ONE", EDN ELECTRICAL DESIGN NEWS, CAHNERS PUBLISHING CO. NEWTON, MASSACHUSETTS, US, (20000217), vol. 45, no. 4, ISSN 0012-7515, pages 67 - 73,75, XP000966353 [A] 1 * the whole document * |