EP1738414 - DUAL-GATE TRANSISTORS [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 26.06.2020 Database last updated on 13.11.2024 | |
Former | Examination is in progress Status updated on 08.05.2018 | Most recent event Tooltip | 26.06.2020 | Application deemed to be withdrawn | published on 29.07.2020 [2020/31] | Applicant(s) | For all designated states Cambridge Enterprise Limited The Old Schools Trinity Lane Cambridge Cambridgeshire CB2 1TN / GB | [2007/27] |
Former [2007/01] | For all designated states Cambridge University Technical Services Limited Research Services Division 16 Mill Lane Cambridge Cambridgeshire CB2 1SB / GB | Inventor(s) | 01 /
CHUA, Lay-Lay Blk 53 Hillview Avenue 02-04 Singapore 669566 / SG | 02 /
HO, Peter, Kian, Hoon BLK 53 Hillview Avenue 02-04 Singapore 669566 / SG | 03 /
FRIEND, Richard, Henry 37 Barton Road Cambridge CB3 9LG / GB | [2007/01] | Representative(s) | Evans, Marc Nigel Page White & Farrer Limited Bedford House 21A John Street London WC1N 2BF / GB | [N/P] |
Former [2007/01] | Evans, Marc Nigel Page White & Farrer Bedford House John Street London, WC1N 2BF / GB | Application number, filing date | 05733049.0 | 05.04.2005 | [2007/01] | WO2005GB01309 | Priority number, date | GB20040007739 | 05.04.2004 Original published format: GB 0407739 | [2007/01] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | WO2005098959 | Date: | 20.10.2005 | Language: | EN | [2005/42] | Type: | A2 Application without search report | No.: | EP1738414 | Date: | 03.01.2007 | Language: | EN | The application published by WIPO in one of the EPO official languages on 20.10.2005 takes the place of the publication of the European patent application. | [2007/01] | Search report(s) | International search report - published on: | EP | 27.04.2006 | Classification | IPC: | H01L29/00 | [2007/01] | CPC: |
H10K19/10 (EP,US);
H10K10/46 (EP,US);
H10K10/462 (EP,US);
H10K10/482 (EP,US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR [2007/01] | Extension states | AL | Not yet paid | BA | Not yet paid | HR | Not yet paid | LV | Not yet paid | MK | Not yet paid | YU | Not yet paid | Title | German: | DOPPELGATE-TRANSISTOREN | [2007/01] | English: | DUAL-GATE TRANSISTORS | [2007/01] | French: | TRANSISTOR DOUBLE GRILLE | [2007/01] | Entry into regional phase | 06.10.2006 | National basic fee paid | 06.10.2006 | Designation fee(s) paid | 06.10.2006 | Examination fee paid | Examination procedure | 06.10.2006 | Examination requested [2007/01] | 01.02.2010 | Despatch of a communication from the examining division (Time limit: M06) | 26.11.2010 | Reply to a communication from the examining division | 30.04.2018 | Despatch of a communication from the examining division (Time limit: M06) | 30.10.2018 | Reply to a communication from the examining division | 18.09.2019 | Despatch of a communication from the examining division (Time limit: M04) | 29.01.2020 | Application deemed to be withdrawn, date of legal effect [2020/31] | 25.02.2020 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2020/31] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 01.02.2010 | Request for further processing for: | The application is deemed to be withdrawn due to failure to reply to the examination report | 26.11.2010 | Request for further processing filed | 26.11.2010 | Full payment received (date of receipt of payment) Request granted | 07.12.2010 | Decision despatched | Fees paid | Renewal fee | 22.01.2007 | Renewal fee patent year 03 | 21.01.2008 | Renewal fee patent year 04 | 03.03.2009 | Renewal fee patent year 05 | 01.03.2010 | Renewal fee patent year 06 | 01.04.2011 | Renewal fee patent year 07 | 08.03.2012 | Renewal fee patent year 08 | 08.03.2013 | Renewal fee patent year 09 | 05.03.2014 | Renewal fee patent year 10 | 10.04.2015 | Renewal fee patent year 11 | 11.04.2016 | Renewal fee patent year 12 | 10.04.2017 | Renewal fee patent year 13 | 10.04.2018 | Renewal fee patent year 14 | 15.04.2019 | Renewal fee patent year 15 | 31.03.2020 | Renewal fee patent year 16 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Licence(s) | ID: | 01 01/exclusive | For: | AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR | Licencee: | Flexenable Limited 34 Cambridge Science Park Milton Road Cambridge Cambridgeshire CB4 0FX / GB | Date: | 11.02.2013 | [2018/21] |
Former [2013/20] | ID: | 01 01/exclusive | |
For: | AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR | ||
Licencee: | PLASTIC LOGIC LIMITED 34 Cambridge Science Park Milton Road Cambridge, Cambridgeshire CB4 0FX / GB | ||
Date: | 11.02.2013 | ||
[2018/21] | Cited in | International search | [Y]GB2064866 (GEN ELECTRIC CO LTD) [Y] 1-14,16,17 * page 1, line 124 - page 2, line 7; figures 5,6 *; | [Y]US5166084 (PFIESTER JAMES R [US]) [Y] 1-14,16,17 * column 5, line 42 - line 53; figure 4 *; | [X]US2002045289 (DIMITRAKOPOULOS CHRISTOS DIMIT [US], et al) [X] 1-6,10,11 * paragraphs [0044] , [0045] , [0047] , [0055]; figure 3 *; | [XY]US2003085398 (KOYAMA TOMOKO [JP], et al) [X] 1-7,10,19 * paragraphs [0109] , [0110]; figures 3A-3C * * paragraphs [0065] - [0067] * [Y] 1-18; | [XY]EP1367659 (SEMICONDUCTOR ENERGY LAB [JP]) [X] 1-4,6,8-10,19 * paragraphs [0034] , [0035]; figures 2A,2B * * paragraphs [0065] - [0067]; figures 7A,7B * [Y] 1-18; | [X]WO2004006633 (MOTOROLA INC [US]) [X] 1-6,8-11 * page 6, lines 5-25; figure 4 * * page 10, lines 6-18 * * page 3, lines 24-29 * * page 11, lines 1-5 *; | [Y] - HERMANN F P ET AL, "A Dynamic Three-State Memory Cell for High-Density Associative Processors", 1990 IEEE SYMPOSIUM ON VLSI CIRCUITS 7-9 JUNE 1990 HONOLULU, HI, USA, IEEE Journal of Solid-State Circuits USA, (199104), vol. 26, no. 4, ISSN 0018-9200, pages 537 - 541, XP002364490 [Y] 18 * figure 2 * DOI: http://dx.doi.org/10.1109/4.75051 | Examination | EP0460242 | JP2004047566 | by applicant | US2003085398 | EP1367659 | US2004006633 |