blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Extract from the Register of European Patents

EP About this file: EP1722304

EP1722304 - Data transfer device which executes DMA transfer, semiconductor integrated circuit device and data transfer method [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  16.01.2009
Database last updated on 24.08.2024
Most recent event   Tooltip16.01.2009Refusal of applicationpublished on 18.02.2009  [2009/08]
Applicant(s)For all designated states
Kabushiki Kaisha Toshiba
1-1 Shibaura 1-chome, Minato-ku
Tokyo 105-8001 / JP
[N/P]
Former [2006/46]For all designated states
KABUSHIKI KAISHA TOSHIBA
1-1 Shibaura 1-chome, Minato-ku
Tokyo 105-8001 / JP
Inventor(s)01 / Haga, Takuya
c/o Toshiba Corp IPD 1-1 Shibaura 1-chome
Minato-ku Tokyo 105-8001 / JP
02 / Azuma, Tetsuhiko
c/o Toshiba Corp IPD 1-1 Shibaura 1-chome
Minato-ku Tokyo 105-8001 / JP
 [2006/46]
Representative(s)Hoffmann Eitle
Patent- und Rechtsanwälte PartmbB
Arabellastrasse 30
81925 München / DE
[N/P]
Former [2006/46]HOFFMANN EITLE
Patent- und Rechtsanwälte Arabellastrasse 4
81925 München / DE
Application number, filing date06009330.905.05.2006
[2006/46]
Priority number, dateJP2005013614909.05.2005         Original published format: JP 2005136149
[2006/46]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1722304
Date:15.11.2006
Language:EN
[2006/46]
Type: A3 Search report 
No.:EP1722304
Date:23.05.2007
[2007/21]
Search report(s)(Supplementary) European search report - dispatched on:EP24.04.2007
ClassificationIPC:G06F13/28
[2006/46]
CPC:
G06F13/28 (EP,US)
Designated contracting statesDE,   FR,   GB [2008/05]
Former [2006/46]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:Datenübertragungsvorrichtung zur Ausführung einer DMA-Übertragung, integrierte Halbleiterschaltung und Datenübertragungsverfahren[2006/46]
English:Data transfer device which executes DMA transfer, semiconductor integrated circuit device and data transfer method[2006/46]
French:Dispositif de transfert de données qui exécute le transfert DMA, dispositif de circuit semi-conducteur intégré et méthode de transfert de données[2006/46]
Examination procedure05.05.2006Examination requested  [2006/46]
23.07.2007Despatch of a communication from the examining division (Time limit: M06)
04.02.2008Reply to a communication from the examining division
29.09.2008Cancellation of oral proceeding that was planned for 09.10.2008
29.09.2008Minutes of oral proceedings despatched
02.10.2008Despatch of communication that the application is refused, reason: substantive examination [2009/08]
09.10.2008Date of oral proceedings
09.10.2008Date of oral proceedings (cancelled)
12.10.2008Application refused, date of legal effect [2009/08]
Fees paidRenewal fee
28.03.2008Renewal fee patent year 03
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XY]US5708849  (COKE JAMES S [US], et al) [X] 1-8,11-20 * figure 2 * * figure 3 * * column 4, line 39 - line 67 * * column 5, line 14 - line 33 * * column 6, line 24 - line 49 * * column 8, line 10 - line 25 * [Y] 9,10;
 [A]US2004030849  (BORKENHAGEN JOHN MICHAEL [US], et al) [A] 9,10* the whole document *;
 [X]US2005027902  (KING MATTHEW EDWARD [US], et al) [X] 1 * paragraph [0014] - paragraph [0015] *;
 [Y]  - RIXNER S ET AL, "MEMORY ACCESS SCHEDULING", COMPUTER ARCHITECTURE NEWS, ACM, NEW YORK, NY, US, (200005), vol. 28, no. 2, ISSN 0163-5964, pages 128 - 138, XP000928722 [Y] 9,10 * page 128, column 2, line 3 - page 129, column 1, line 4 * * figure 1 *

DOI:   http://dx.doi.org/10.1145/342001.339668
 [Y]  - CORBAL J ET AL, "Command vector memory systems: high performance at low cost", PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 1998. PROCEEDINGS. 1998 INTERNATIONAL CONFERENCE ON PARIS, FRANCE 12-18 OCT. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19981012), ISBN 0-8186-8591-3, pages 68 - 77, XP010312254 [Y] 9,10 * paragraph [04.2] * * paragraph [04.3]; figure 6 *

DOI:   http://dx.doi.org/10.1109/PACT.1998.727154
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.