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EP1708205
European procedure
Extract from the Register of European Patents
EP About this file: EP1708205
| EP1708205 - Ram testing apparatus and method [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 20.02.2009 Database last updated on 03.09.2024 | Most recent event Tooltip | 20.02.2009 | No opposition filed within time limit | published on 25.03.2009 [2009/13] | Applicant(s) | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | [N/P] |
| Former [2006/40] | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | Inventor(s) | 01 /
Satsukawa, Yoshihiko, c/o Fujitsu Limited 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | 02 /
Watanabe, Hisashi, c/o Fujitsu Limited 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | [2006/40] | Representative(s) | Hitching, Peter Matthew, et al Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [2008/41] | Hitching, Peter Matthew, et al Haseltine Lake Lincoln House 300 High Holborn London WC1V 7JH / GB | ||
| Former [2006/40] | Hitching, Peter Matthew, et al HASELTINE LAKE Imperial House 15-19 Kingsway London WC2B 6UD / GB | Application number, filing date | 06250627.4 | 06.02.2006 | [2006/40] | Priority number, date | JP20050088821 | 25.03.2005 Original published format: JP 2005088821 | [2006/40] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1708205 | Date: | 04.10.2006 | Language: | EN | [2006/40] | Type: | B1 Patent specification | No.: | EP1708205 | Date: | 16.04.2008 | Language: | EN | [2008/16] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.06.2006 | Classification | IPC: | G11C29/00 | [2006/40] | CPC: |
G11C29/44 (EP,US);
G11C29/38 (EP,US);
G11C2029/0405 (EP,US);
G11C2029/1208 (EP,US);
G11C2029/3202 (EP,US);
G11C2029/3602 (EP,US)
| Designated contracting states | DE, FR, GB [2007/24] |
| Former [2006/40] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Vorrichtung und Verfahren zur Prüfung einer RAM | [2006/40] | English: | Ram testing apparatus and method | [2006/40] | French: | Circuit et procédé de test pour mémoire RAM | [2006/40] | Examination procedure | 02.04.2007 | Examination requested [2007/20] | 04.05.2007 | Despatch of a communication from the examining division (Time limit: M04) | 01.08.2007 | Reply to a communication from the examining division | 21.09.2007 | Communication of intention to grant the patent | 16.01.2008 | Fee for grant paid | 16.01.2008 | Fee for publishing/printing paid | Opposition(s) | 19.01.2009 | No opposition filed within time limit [2009/13] | Fees paid | Renewal fee | 27.02.2008 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DA]JPH1139226 ; | [A]WO0101422 (ISD LISIS OLOKLIROMENON SISTIM [GR], et al); | [A]US6523135 (NAKAMURA YOSHIYUKI [JP]) | [DA] - PATENT ABSTRACTS OF JAPAN, (19990531), vol. 1999, no. 05, & JP11039226 A 19990212 (TOSHIBA CORP) [DA] 1-9 * abstract * | by applicant | JPH1139226 |