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EP1696273
European procedure
Extract from the Register of European Patents
EP About this file: EP1696273
| EP1696273 - Method and apparatus for optimising illumination for full-chip layer [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.06.2009 Database last updated on 31.08.2024 | Most recent event Tooltip | 12.06.2009 | No opposition filed within time limit | published on 15.07.2009 [2009/29] | Applicant(s) | For all designated states ASML MaskTools B.V. De Run 6501 5504 DR Veldhoven / NL | [2006/35] | Inventor(s) | 01 /
Socha, Robert 137 Monte Villa Court Campbell CA 95008 / US | 02 /
Chen, Jang Fung 11752 Pine Brook Lane Cupertino, CA 95014 / US | [2006/35] | Representative(s) | van den Hooven, Jan, et al ASML Netherlands B.V. Corporate Intellectual Property P.O. Box 324 5500 AH Veldhoven / NL | [N/P] |
| Former [2009/14] | Van den Hooven, Jan, et al ASML Netherlands B.V. Corporate Intellectual Property P.O. Box 324 5500 AH Veldhoven / NL | ||
| Former [2006/35] | Leeming, John Gerard J.A. Kemp & Co., 14 South Square, Gray's Inn London WC1R 5JJ / GB | Application number, filing date | 06250911.2 | 21.02.2006 | [2006/35] | Priority number, date | US20050654962P | 23.02.2005 Original published format: US 654962 P | [2006/35] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1696273 | Date: | 30.08.2006 | Language: | EN | [2006/35] | Type: | A3 Search report | No.: | EP1696273 | Date: | 18.07.2007 | [2007/29] | Type: | B1 Patent specification | No.: | EP1696273 | Date: | 06.08.2008 | Language: | EN | [2008/32] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.06.2007 | Classification | IPC: | G03F7/20 | [2006/35] | CPC: |
G03F7/705 (EP,KR,US);
G03F7/70125 (EP,KR,US);
G03F1/36 (KR)
| Designated contracting states | DE, FR, GB, IT, NL [2008/13] |
| Former [2006/35] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Methode und Apparat zur Optimierung der Beleuchtung einer Schicht eines vollständigen Chips | [2006/35] | English: | Method and apparatus for optimising illumination for full-chip layer | [2006/35] | French: | Méthode et appareil pour optimiser l'illumination d'une couche de puce en entier | [2006/35] | Examination procedure | 24.10.2007 | Examination requested [2007/49] | 07.02.2008 | Communication of intention to grant the patent | 17.06.2008 | Fee for grant paid | 17.06.2008 | Fee for publishing/printing paid | Opposition(s) | 07.05.2009 | No opposition filed within time limit [2009/29] | Fees paid | Renewal fee | 14.02.2008 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP2000243690 (NEC CORP) [A] 1-23 * abstract * * claim 1 *; | [A]US2005015233 (GORDON RONALD L [US]) [A] 1-23 * abstract * * paragraphs [0010] , [0011] , [0014] * * claim 1 *; | [A]EP1473596 (ASML NETHERLANDS BV [NL]) [A] 1-23 * abstract * * figures 13,14a,14b * | by applicant | US6046792 | US5969441 | - M. BORN; E. WOLF, PRINCIPLES OF OPTICS, PERGAMON PRESS, vol. 530 |