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Extract from the Register of European Patents

EP About this file: EP1770509

EP1770509 - Scheduling in a multicore artchitecture [Right-click to bookmark this link]
Status	The application has been refused Status updated on 02.09.2016 Database last updated on 13.11.2024
Most recent event Tooltip	02.09.2016	Refusal of application	published on 05.10.2016 [2016/40]
Applicant(s)	For all designated states Synopsys, Inc. 690 East Middlefield Road Mountain View, CA 94043 / US
	For all designated states Fujitsu Semiconductor Limited 2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi Kanagawa 222-0033 / JP
	[2015/12]
Former [2012/33]	For all designated states Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 / US
	For all designated states Fujitsu Semiconductor Limited 2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi Kanagawa 222-0033 / JP
Former [2012/03]	For all designated states Coware, Inc. 1732 North First Street San Jose, CA 95112 / US
	For all designated states Fujitsu Semiconductor Limited 2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi Kanagawa 222-0033 / JP
Former [2009/15]	For all designated states Coware, Inc. 1732 North First Street San Jose, CA 95112 / US
	For all designated states Fujitsu Microelectronics Limited 7-1, Nishi-Shinjuku 2-chome Shinjuku-ku Tokyo 163-0722 / JP
Former [2007/14]	For all designated states Coware, Inc. 1732 North First Street San Jose, CA 95112 / US
	For all designated states Fujitsu Ltd. 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 / JP
Inventor(s)	01 / Lippett, Mark David 18 Stoner Green, Watlington Oxfordshire OX49 5PT / GB
	[2007/14]
Representative(s)	Boult Wade Tennant LLP Salisbury Square House 8 Salisbury Square London EC4Y 8AP / GB
	[N/P]
Former [2013/51]	Boult Wade Tennant Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB
Former [2007/14]	Frost, Alex John Boult Wade Tennant, Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB
Application number, filing date	06254991.0	27.09.2006
	[2007/14]
Priority number, date	GB20050019981	30.09.2005 Original published format: GB 0519981
	[2007/14]
Filing language	EN
Procedural language	EN
Publication	Type:	A2 Application without search report
	No.:	EP1770509
	Date:	04.04.2007
	Language:	EN
	[2007/14]
	Type:	A3 Search report
	No.:	EP1770509
	Date:	07.05.2008
	[2008/19]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	08.04.2008
Classification	IPC:	G06F9/40	[2007/14]
	CPC:	G06F1/3203 (EP,US); G06F9/46 (KR); G06F15/80 (US); G06F9/38 (KR); G06F9/466 (US); G06F9/4893 (EP,US); (+) G06F9/5027 (US); G06F9/5038 (US); G06F2209/483 (EP,US); G06F2209/5011 (EP,US); Y02D10/00 (EP,US) (-)
Designated contracting states	DE, FR, GB, IT [2009/03]
Former [2007/14]	AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR
Title	German:	Planung bei einer mehradrigen Architektur	[2007/14]
	English:	Scheduling in a multicore artchitecture	[2007/14]
	French:	Planification dans une architecture multicýur	[2007/14]
Examination procedure	17.09.2008	Examination requested [2008/44]
	08.11.2008	Loss of particular rights, legal effect: designated state(s)
	12.11.2008	Despatch of a communication from the examining division (Time limit: M06)
	16.12.2008	Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GR, HU, IE, IS, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR
	21.05.2009	Reply to a communication from the examining division
	14.10.2014	Despatch of a communication from the examining division (Time limit: M04)
	11.02.2015	Reply to a communication from the examining division
	15.05.2015	Despatch of a communication from the examining division (Time limit: M04)
	24.09.2015	Reply to a communication from the examining division
	29.03.2016	Application refused, date of legal effect [2016/40]
	29.03.2016	Date of oral proceedings
	09.05.2016	Despatch of communication that the application is refused, reason: substantive examination [2016/40]
Divisional application(s)	EP10192097.3 / EP2328076
	EP10192098.1 / EP2328077
	EP10192099.9 Application deemed to be withdrawn : 23.12.2010
	The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 12.11.2008
Fees paid	Renewal fee
	23.09.2008	Renewal fee patent year 03
	23.09.2009	Renewal fee patent year 04
	27.09.2010	Renewal fee patent year 05
	23.09.2011	Renewal fee patent year 06
	24.09.2012	Renewal fee patent year 07
	23.09.2013	Renewal fee patent year 08
	23.09.2014	Renewal fee patent year 09
	23.09.2015	Renewal fee patent year 10
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:	Search	[A]US5566340 (STEWART GREGORY N [US], et al) [A] 23 * column 1, line 63 - column 2, line 10 *;
		[X]US2003014743 (COOKE LAURENCE H [US], et al) [X] 29,44 * page 3, paragraph 32 * * page 4, paragraph 35 *;
		[X]US2003056091 (GREENBERG CRAIG B [US]) [X] 29,44 * page 1, paragraph 3 - paragraph 4 * * page 2, paragraph 28 - paragraph 30 *;
		[X]US6711691 (HOWARD BRIAN D [US], et al) [X] 22,23,25,26,43 * column 2, line 7 - line 30 * * column 5, line 17 - column 6, line 27 * * column 8, line 23 - line 33 *;
		[A]US2004128563 (KAUSHIK SHIVNANDAN D [US], et al) [A] 22,23,25,26,43 * the whole document *;
		[A]US2004268354 (KANAI TATSUNORI [JP], et al) [A] 1-21,24,27,28,30-42,45,46 * the whole document *;
		[X]US2005166074 (HACK MARK E [US]) [X] 22,23,25,26,43 * abstract * * page 1, paragraph 10 * * page 4, paragraph 38 - paragraph 39 * * page 4, paragraph 43 *;
		[A]US2005210304 (HARTUNG STEVEN F [US], et al) [A] 26 * page 1, paragraph 9 *;
		[X] - J.D. REGEHR, "Using Hierarchical Scheduling to Support Soft Real-Time Applications in General-Purpose Operating Systems", (200105), URL: http://www.cs.utah.edu/~regehr/papers/diss/regehr-diss-single.pdf, (20071214), XP002462619 [X] 1-21,24,27,28,30-42,45,46 * page 3, paragraph 1.3 * * page 4 * * page 16, paragraph 2.3.1.6 - page 17 * * page 68, paragraph 6.2 *
		[A] - BOUCHHIMA A ET AL, "Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model", ASP-DAC 2004: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2004 (IEEE CAT. NO.04EX753) IEEE PISCATAWAY, NJ, USA, (2004), ISBN 0-7803-8175-0, pages 469 - 474, XP002462620 [A] 1-21,24,27,28,30-42,45,46 * the whole document * DOI: http://dx.doi.org/10.1109/ASPDAC.2004.1337621
		[A] - LIAO ET AL, "Evaluating OpenMP on chip multithreading platforms", (20050706), URL: http://www2.cs.uh.edu/Preprints/preprint/uh-cs-05-12.pdf, (20071217), XP002462621 [A] 1-21,24,27,28,30-42,45,46 * the whole document *
		[A] - TIEN-FU CHEN ET AL, "Flexible heterogeneous multicore architectures for versatile media processing via customized long instruction words", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY IEEE USA, (200505), vol. 15, no. 5, ISSN 1051-8215, pages 659 - 672, XP002473436 [A] 29,44 * the whole document * DOI: http://dx.doi.org/10.1109/TCSVT.2005.846442
		[A] - C. SULLIVAN, A. WILSON, S. CHAPPELL, "Deterministic Hardware Synthesis for Compiling High-Level Descriptions to Heterogeneous Reconfigurable Architectures", ISSN 15301605, ISBN 0769522688, (20050106), URL: http://ieeexplore.ieee.org/iel5/9518/30166/01385854.pdf?tp=&isnumber=&arnumber=1385854, (20080319), XP002473437 [A] 29,44 * the whole document *
		[A] - CLARK, NATHUJI, LEE, "Using an FPGA as a Prototyping Platform for Multi-core Processor Applications", (20050213), URL: http://www.cag.csail.mit.edu/warfp2005/submissions/30-clark.pdf, (20080319), XP002473438 [A] 29,44 * the whole document *

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