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Extract from the Register of European Patents

EP About this file: EP1753275

EP1753275 - Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  22.10.2010
Database last updated on 05.07.2024
Most recent event   Tooltip22.10.2010Application deemed to be withdrawnpublished on 24.11.2010  [2010/47]
Applicant(s)For all designated states
Alcatel Lucent
54, rue la Boétie
75008 Paris / FR
[N/P]
Former [2007/15]For all designated states
Alcatel Lucent
54 rue La Boétie
75008 Paris / FR
Former [2007/07]For all designated states
Alcatel
54, rue La Boétie
75008 Paris / FR
Inventor(s)01 / Brown, Paul James
P.O. Box 5
Wakefield Québec J0X 3G0 / CA
 [2007/07]
Representative(s)Hervouet-Malbec, Sylvie, et al
Ipsilon
Le Centralis
63, avenue du Général Leclerc
92340 Bourg-la-Reine / FR
[N/P]
Former [2007/07]Hervouet, Sylvie, et al
Feray Lenne Conseil, 39/41, avenue Aristide Briand
92163 Anthony Cedex / FR
Application number, filing date06300874.210.08.2006
[2007/07]
Priority number, dateUS2005020004110.08.2005         Original published format: US 200041
[2007/07]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1753275
Date:14.02.2007
Language:EN
[2007/07]
Type: A3 Search report 
No.:EP1753275
Date:21.01.2009
[2009/04]
Search report(s)(Supplementary) European search report - dispatched on:EP23.12.2008
ClassificationIPC:H05K1/11, // H01L23/498
[2007/07]
CPC:
H01L23/49816 (EP,US); H01L23/49827 (EP,US); H01L23/49838 (EP,US);
H01L23/50 (EP,US); H05K1/114 (EP,US); H01L2924/0002 (EP,US);
H05K2201/09227 (EP,US); H05K2201/09509 (EP,US); H05K2201/10734 (EP,US);
H05K3/429 (EP,US) (-)
C-Set:
H01L2924/0002, H01L2924/00 (EP,US)
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2007/07]
TitleGerman:Benutzung von der Reihen/Kolonnen von Mikro- vias in einem BGA-Verbindungsgitter für einen optimierten Leiterbahnenverlauf[2007/07]
English:Using rows/columns of micro-vias in a BGA interconnect grid to create improved PCB routing channels[2007/07]
French:Utilisation des rangées/colonnes de micro-vias dans une grille d'interconnexion BGA pour créer des pistes de circuit imprimé optimisées[2007/07]
Examination procedure21.07.2009Examination requested  [2009/35]
30.10.2009Despatch of a communication from the examining division (Time limit: M06)
11.05.2010Application deemed to be withdrawn, date of legal effect  [2010/47]
15.06.2010Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2010/47]
Fees paidRenewal fee
19.08.2008Renewal fee patent year 03
24.08.2009Renewal fee patent year 04
Penalty fee
Additional fee for renewal fee
31.08.201005   M06   Not yet paid
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[X]US6198635  (SHENOY JAYARAMA N [US], et al) [X] 1-3,4,5 * column 4, line 38 - column 8, line 51; figures 2-7 * * figure 9 *;
 [X]US6207476  (ZHAO LILY [US], et al) [X] 4,5 * column 3, line 26 - column 4, line 65; figures 1,2 *;
 [A]US6232564  (ARNDT STEVEN FREDERICK [US], et al) [A] 1-3 * abstract *;
 [X]US6388890  (KWONG HERMAN [CA], et al) [X] 1-3 * the whole document *;
 [X]EP1347674  (NORTEL NETWORKS LTD [CA]) [X] 1-3 * the whole document *;
 [X]EP1361612  (TOSHIBA KK [JP]) [X] 4,5* paragraph [0012]; figure 5 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.