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Extract from the Register of European Patents

EP About this file: EP1876523

EP1876523 - Computation of A MOD (2^n - 1) [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  23.07.2010
Database last updated on 13.11.2024
Most recent event   Tooltip23.07.2010Refusal of applicationpublished on 25.08.2010  [2010/34]
Applicant(s)For all designated states
VIA Telecom Co., Ltd.
Zephyr House
Mary Street
P.O. Box 709
George Town
Grand Cayman, British West Indies / KY
[N/P]
Former [2008/02]For all designated states
VIA Telecom Co., Ltd.
Zephyr House, Mary Street, PO Box 709 George Town
Grand Cayman, British West Indies / KY
Inventor(s)01 / Shen, Qiang
7689 Pipit Place San Diego
California 92129 / US
 [2008/02]
Representative(s)Käck, Jürgen
Patentanwälte
Kahler Käck Mollekopf
Vorderer Anger 239
86899 Landsberg/Lech / DE
[N/P]
Former [2008/02]Käck, Jürgen
Kahler Käck Mollekopf Vorderer Anger 239
D-86899 Landsberg/Lech / DE
Application number, filing date07013265.906.07.2007
[2008/02]
Priority number, dateUS2006045611007.07.2006         Original published format: US 456110
[2008/02]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1876523
Date:09.01.2008
Language:EN
[2008/02]
Search report(s)(Supplementary) European search report - dispatched on:EP23.10.2007
ClassificationIPC:G06F7/72
[2008/02]
CPC:
G06F7/727 (EP,US)
Designated contracting statesDE,   FR,   GB [2008/38]
Former [2008/02]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MT,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:Berechnung von A MOD (2^n - 1)[2008/02]
English:Computation of A MOD (2^n - 1)[2008/02]
French:Calcul de A MOD (2^n - 1)[2008/02]
Examination procedure08.02.2008Amendment by applicant (claims and/or description)
08.02.2008Examination requested  [2008/12]
10.07.2008Loss of particular rights, legal effect: designated state(s)
18.08.2008Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR
20.02.2009Despatch of a communication from the examining division (Time limit: M04)
29.05.2009Reply to a communication from the examining division
16.03.2010Date of oral proceedings
31.03.2010Minutes of oral proceedings despatched
06.04.2010Despatch of communication that the application is refused, reason: substantive examination [2010/34]
16.04.2010Application refused, date of legal effect [2010/34]
Fees paidRenewal fee
29.07.2009Renewal fee patent year 03
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Documents cited:Search[YA]EP0318957  (FUJITSU LTD [JP]) [Y] 8 * column 4, line 43 - column 5, line 12; figure 1 * [A] 6,14;
 [A]FR2786579  (ST MICROELECTRONICS SA [FR]) [A] 4,9,18,20* figures 3,7 *;
 [XY]  - RANADE A G ED - DEGROOT D INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, "INTERCONNECTION NETWORKS AND PARALLEL MEMORY ORGANIZATIONS FOR ARRAY PROCESSING", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING. AUGUST 20 - 23, 1985, WASHINGTON, IEEE COMP.SOC.PRESS, US, (198508), pages 41 - 47, XP000757117 [X] 1-7,9-24 * page 43, column L, line 26 - column R, line 18; figure 1 * [Y] 8
 [A]  - SIVAKUMAR R ET AL, "VLSI design of a modulo-extractor", COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, 1991., IEEE PACIFIC RIM CONFERENCE ON VICTORIA, BC, CANADA 9-10 MAY 1991, NEW YORK, NY, USA,IEEE, US, (19910509), ISBN 0-87942-638-1, pages 327 - 330, XP010039443 [A] 1,2,6,14,19 * figure 1 * * sections 2.2 and 3.2.1 *

DOI:   http://dx.doi.org/10.1109/PACRIM.1991.160745
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.