-
EP1840742
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP1840742
| EP1840742 - Method and apparatus for operating a computer processor array [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 12.08.2011 Database last updated on 19.10.2024 | Most recent event Tooltip | 12.08.2011 | Application deemed to be withdrawn | published on 14.09.2011 [2011/37] | Applicant(s) | For all designated states VNS Portfolio LLC 20400 Stevens Creek Boulevard Fifth Floor Cupertino, CA 95014 / US | [2009/34] |
| Former [2008/36] | For all designated states VNS Portfolio LLC 20400 Stevens Creek Blvd Suite 500 Cupertino, CA 95014 / US | ||
| Former [2007/40] | For all designated states Technology Properties Limited 20400 Stevens Creek Blvd Suite 500 Cupertino CA 95014 / US | Inventor(s) | 01 /
Moore, Charles H. 110 Greene Road Sierra City California 96125 / US | 02 /
Fox, Jeffrey Arthur 2512 10th Street Berkeley California 94710 / US | 03 /
Rible, John W. 317 California Street Santa Cruz California 95060-4215 / US | [2007/40] | Representative(s) | Beresford, Keith Denis Lewis Beresford Crump LLP 16 High Holborn London WC1V 6BX / GB | [N/P] |
| Former [2007/40] | Beresford, Keith Denis Lewis BERESFORD & Co. 16 High Holborn London WC1V 6BX / GB | Application number, filing date | 07251416.9 | 30.03.2007 | [2007/40] | Priority number, date | US20060788265P | 31.03.2006 Original published format: US 788265 P | [2007/40] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1840742 | Date: | 03.10.2007 | Language: | EN | [2007/40] | Type: | A3 Search report | No.: | EP1840742 | Date: | 26.11.2008 | [2008/48] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.10.2008 | Classification | IPC: | G06F9/46, G06F15/163, G06F15/80 | [2007/40] | CPC: |
G06F15/8023 (EP,US);
G06F15/163 (KR);
G06F15/16 (KR);
G06F15/173 (KR);
G06F9/5066 (EP,US);
G06F9/547 (EP,US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR [2007/40] | Title | German: | Verfahren und Vorrichtung zum Bedienen eines Computerprozessor-Arrays | [2007/40] | English: | Method and apparatus for operating a computer processor array | [2007/40] | French: | Procédé et appareil pour faire fonctionner un réseau de processeur informatique | [2007/40] | Examination procedure | 20.05.2009 | Examination requested [2009/27] | 22.05.2009 | Amendment by applicant (claims and/or description) | 15.07.2009 | Despatch of a communication from the examining division (Time limit: M06) | 14.12.2009 | Reply to a communication from the examining division | 10.09.2010 | Despatch of a communication from the examining division (Time limit: M06) | 22.03.2011 | Application deemed to be withdrawn, date of legal effect [2011/37] | 26.04.2011 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2011/37] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 15.07.2009 | Fees paid | Renewal fee | 19.03.2009 | Renewal fee patent year 03 | 15.04.2010 | Renewal fee patent year 04 | 15.03.2011 | Renewal fee patent year 05 | Penalty fee | Additional fee for renewal fee | 31.03.2010 | 04 M06 Fee paid on 15.04.2010 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US5317735 (SCHOMBERG HERMANN [DE]) [X] 10-14 * column 1, lines 37-53 * * column 6, lines 9-14 * * column 8, lines 56-68 * * column 10, line 48 *; | [Y]EP1182544 (SUN MICROSYSTEMS INC [US]) [Y] 6 * paragraphs [0010] - [0016] *; | [XY]WO2005091847 (TECHNOLOGY PROPERTIES LTD [US], et al) [X] 1,15,20,21,24,25,27 * page 4; figure 1 * * page 9 * * page 11, line 1 * * page 2, lines 13-16 * [Y] 2-9; | [X] - PALMER J ET AL, "Connection Machine model CM-5 system overview", FRONTIERS OF MASSIVELY PARALLEL COMPUTATION, 1992., FOURTH SYMPOSIUM ON THE MCLEAN, VA, USA 19-21 OCT. 1992, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19921019), ISBN 0-8186-2772-7, pages 474 - 483, XP010028478 [X] 1,15,20,21,24,27 * the whole document * DOI: http://dx.doi.org/10.1109/FMPC.1992.234877 | [Y] - MAJURSKI W ET AL, "Flits: pervasive computing for processor and memory constrained systems", PARALLEL PROCESSING, 2000. PROCEEDINGS. 2000 INTERNATIONAL WORKSHOPS ON 21-24 AUGUST 2000, PISCATAWAY, NJ, USA,IEEE, (20000821), ISBN 0-7695-0771-9, pages 31 - 38, XP010511930 [Y] 2-9 * pages 33-36 * DOI: http://dx.doi.org/10.1109/ICPPW.2000.869084 | [A] - THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC., "IEEE Standard for Boot (Initialization Configuration) Firmware: Core Requirements and Practices", IEEE STANDARDS, New York, USA, (1994), ISBN 1-55937-426-8, pages 1 - 104, XP002444849 [A] 1,15,20,21,24,27 * the whole document * | [X] - SCHMIDT U ET AL, "DATAWAVE: A SINGLE-CHIP MULTIPROCESSOR FOR VIDEO APPLICATIONS", IEEE MICRO, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, (19910601), vol. 11, no. 3, ISSN 0272-1732, pages 22 - 25,88, XP000237234 [X] 22,26 * page 23, column L, paragraph L * * page 23, column R, paragraph 1; figure 1 * * page 24, column R, paragraph 2 * * page 90, column R, paragraph 4 * * page 91, column L; figure 9 * DOI: http://dx.doi.org/10.1109/40.87567 | [A] - VENNERS B, "CHAPTER 1 INTRODUCTION TO JAVA'S ARCHITECTURE", INSIDE THE JAVA 2.0 VIRTUAL MACHINE, (19990801), pages 1 - 10, XP000962224 [A] 2-9 * the whole document * | [X] - AGARWAL A ET AL, "The raw microprocessor: a computational fabric for software circuits and general-purpose programs", IEEE MICRO, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, (20020301), vol. 22, no. 2, ISSN 0272-1732, pages 25 - 35, XP011094422 [X] 16-18 * paragraph bridging pages 26, 27 * * page 28, column L, paragraph L; figure 2 * * page 29, column R, paragraph L; figure 3 * | [X] - KANG Y ET AL, "Use IRAM for rasterization", IMAGE PROCESSING, 1998. ICIP 98. PROCEEDINGS. 1998 INTERNATIONAL CONFE RENCE ON CHICAGO, IL, USA 4-7 OCT. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19981004), vol. 3, ISBN 978-0-8186-8821-8, pages 1010 - 1013, XP010586951 [X] 19 * page 1010, right-hand column, penultimate paragraph * * page 1011, right-hand column, penultimate paragraph * * page 1012, column L, paragraph 2 * DOI: http://dx.doi.org/10.1109/ICIP.1998.999085 | [X] - ZHIYI YU ET AL, "Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems", EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006. IEEE COMPUTER SOCI ETY ANNUAL SYMPOSIUM ON KLARLSRUHE, GERMANY 02-03 MARCH 2006, PISCATAWAY, NJ, USA,IEEE, (20060302), ISBN 978-0-7695-2533-4, pages 378 - 383, XP010898670 [X] 23 * page 2, column L, paragraph 2 - column R, paragraph 3; figures 3-5 * DOI: http://dx.doi.org/10.1109/ISVLSI.2006.72 | [A] - RATHER E D ET AL, "The evolution of Forth", SIGPLAN NOTICES USA, (199303), vol. 28, no. 3, ISSN 0362-1340, pages 177 - 199, XP002498798 [A] 1-27 * the whole document * DOI: http://dx.doi.org/10.1145/155360.155369 | Examination | WO0042506 | - David Flanagan, Jim Farley, William Crawford and Kris Magnusson, Java (TM) Enterprise in a Nutshell - Chapter 7.7, USA, O'Reilly & Associates, (2001), ISBN 1-56592-483-5, XP002598506 | by applicant | US5317735 | WO0042506 | WO2005091847 | - PALMER J ET AL., "Connection Machine model CM-5 system overview", FRONTIERS OF MASSIVELY PARALLEL COMPUTATION, FOURTH SYMPOSIUM ON THE MCLEAN, 19-21 OCT. 1992, LOS ALAMITOS, CA, USA, IEEE COMPUT. SOC, (20001019), pages 474 - 483 | - MAJURSKI W ET AL., "Flits: pervasive computing for processor and memory constrained systems", PARALLEL PROCESSING, PROCEEDINGS INTERNATIONAL WORKSHOPS ON 21-24 AUGUST 2000, PISCATAWAY, NJ, USA,IEEE, (20000821), pages 31 - 38 |