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Extract from the Register of European Patents

EP About this file: EP2002475

EP2002475 - METHOD FOR PRODUCING AN INTEGRATED CIRCUIT [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  10.03.2017
Database last updated on 17.09.2024
Most recent event   Tooltip10.07.2020Lapse of the patent in a contracting state
New state(s): IS		published on 12.08.2020  [2020/33]
Applicant(s)For all designated states
INSTITUT FÜR MIKROELEKTRONIK STUTTGART
Allmandring 30a
70569 Stuttgart / DE
[2008/51]
Inventor(s)01 / BURGHARTZ, Joachim, N.
Teckstrasse 3
70771 Leinfelden-Echterdingen / DE
02 / ZIMMERMANN, Martin
Haeberlinstr. 19
70563 Stuttgart / DE
03 / APPEL, Wolfgang
Richard-Wagner Str. 40
71701 Schwieberdingen / DE
 [2008/51]
Representative(s)Witte, Weller & Partner Patentanwälte mbB
Postfach 10 54 62
70047 Stuttgart / DE
[2016/18]
Former [2008/51]Duhme, Torsten, et al
Witte, Weller & Partner Patentanwälte Postfach 10 54 62
70047 Stuttgart / DE
Application number, filing date07723044.906.03.2007
[2008/51]
WO2007EP01886
Priority number, dateDE2006101341914.03.2006         Original published format: DE102006013419
DE2006105939408.12.2006         Original published format: DE102006059394
[2008/51]
Filing languageDE
Procedural languageDE
PublicationType: A1 Application with search report
No.:WO2007104443
Date:20.09.2007
Language:DE
[2007/38]
Type: A1 Application with search report 
No.:EP2002475
Date:17.12.2008
Language:DE
The application published by WIPO in one of the EPO official languages on 20.09.2007 takes the place of the publication of the European patent application.
[2008/51]
Type: B1 Patent specification 
No.:EP2002475
Date:04.05.2016
Language:DE
[2016/18]
Search report(s)International search report - published on:EP20.09.2007
ClassificationIPC:H01L21/78, H01L21/304, H01L21/02
[2014/48]
CPC:
H01L21/7813 (EP,US); H01L21/78 (KR); H01L21/02002 (EP,US)
Former IPC [2008/51]H01L21/78
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MT,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2016/18]
Former [2008/51]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MT,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
Extension statesALNot yet paid
BANot yet paid
HRNot yet paid
MKNot yet paid
RSNot yet paid
TitleGerman:VERFAHREN ZUM HERSTELLEN EINER INTEGRIERTEN SCHALTUNG[2008/51]
English:METHOD FOR PRODUCING AN INTEGRATED CIRCUIT[2008/51]
French:PROCÉDÉ POUR PRODUIRE UN CIRCUIT INTÉGRÉ[2008/51]
Entry into regional phase18.09.2008National basic fee paid 
18.09.2008Designation fee(s) paid 
18.09.2008Examination fee paid 
Examination procedure18.09.2008Examination requested  [2008/51]
03.07.2012Despatch of a communication from the examining division (Time limit: M06)
03.07.2012Invitation to provide information on prior art
06.08.2012Reply to the invitation to provide information on prior art
19.02.2013Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time
23.04.2013Reply to a communication from the examining division
09.12.2014Despatch of a communication from the examining division (Time limit: M02)
19.02.2015Reply to a communication from the examining division
08.10.2015Communication of intention to grant the patent
18.02.2016Fee for grant paid
18.02.2016Fee for publishing/printing paid
18.02.2016Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  03.07.2012
Opposition(s)07.02.2017No opposition filed within time limit [2017/15]
Request for further processing for:The application is deemed to be withdrawn due to failure to reply to the examination report
23.04.2013Request for further processing filed
23.04.2013Full payment received (date of receipt of payment)
Request granted
10.05.2013Decision despatched
Fees paidRenewal fee
18.09.2008Renewal fee patent year 03
25.03.2010Renewal fee patent year 04
23.03.2011Renewal fee patent year 05
21.03.2012Renewal fee patent year 06
20.03.2013Renewal fee patent year 07
25.03.2014Renewal fee patent year 08
18.03.2015Renewal fee patent year 09
23.03.2016Renewal fee patent year 10
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU06.03.2007
BG04.05.2016
CY04.05.2016
CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
MT04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
TR04.05.2016
GR05.08.2016
IS04.09.2016
PT05.09.2016
[2020/33]
Former [2020/15]HU06.03.2007
BG04.05.2016
CY04.05.2016
CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
MT04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
TR04.05.2016
GR05.08.2016
PT05.09.2016
Former [2019/46]HU06.03.2007
BG04.05.2016
CY04.05.2016
CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
MT04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2019/39]HU06.03.2007
BG04.05.2016
CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
MT04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2019/31]HU06.03.2007
CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
MT04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2018/43]CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
MT04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2018/01]CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
MC04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2017/37]CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SI04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2017/10]CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
PL04.05.2016
RO04.05.2016
SE04.05.2016
SK04.05.2016
GR05.08.2016
PT05.09.2016
Former [2017/09]CZ04.05.2016
DK04.05.2016
EE04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
RO04.05.2016
SE04.05.2016
GR05.08.2016
PT05.09.2016
Former [2017/07]DK04.05.2016
ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
SE04.05.2016
GR05.08.2016
PT05.09.2016
Former [2016/52]ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
SE04.05.2016
GR05.08.2016
PT05.09.2016
Former [2016/51]ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
GR05.08.2016
PT05.09.2016
Former [2016/50]ES04.05.2016
FI04.05.2016
LT04.05.2016
LV04.05.2016
Former [2016/49]FI04.05.2016
LT04.05.2016
Former [2016/46]LT04.05.2016
Cited inInternational search[X]FR2823596  (COMMISSARIAT ENERGIE ATOMIQUE [FR]) [X] 1,3,8,11 * abstract * * page 39 - page 41 *;
 [A]US6774010  (CHU JACK OON [US], et al) [A] 1-14 * column 5, line 48 - column 6, line 67 *;
 [A]DE10019705  (MITSUBISHI ELECTRIC CORP [JP]) [A] 4-7,11 * figure - *
by applicantUS2005029224
 DE4029973
 WO2005104223
 US6165813
 US6521068
 JP2002299500
 DE19752208
 US6774010
 DE10019705
    - OVERSTOLZ ET AL., "A Clean Wafer-Scale Chip-Release Process without Dicing Based on Vapor Phase Etching", 17TH IEEE INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS, (200401), pages 717 - 720
    - ARMBRUSTER ET AL., "Surface Micromachining of Monocrystalline Silicon Membranes Using a Silicon Micro Grid of Sintered Porous Silicon", TECHNICAL DIGEST OF EUROSENSORS XVIII, (20040912), page 22,23
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.