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EP2075839
European procedure
Extract from the Register of European Patents
EP About this file: EP2075839
| EP2075839 - METHOD FOR EVALUATING SOI WAFER [Right-click to bookmark this link] | |||
| Former [2009/27] | METHOD FOR EVALUATING SEMICONDUCTOR WAFER | ||
| [2010/51] | Status | No opposition filed within time limit Status updated on 16.03.2012 Database last updated on 06.07.2024 | Most recent event Tooltip | 16.03.2012 | No opposition filed within time limit | published on 18.04.2012 [2012/16] | Applicant(s) | For all designated states Shin-Etsu Handotai Co., Ltd. 6-2, Ohtemachi 2-chome Chiyoda-ku Tokyo 100-0004 / JP | [2009/27] | Inventor(s) | 01 /
OHTSUKI, Tsuyoshi Isobe R & D Center, Shin-Etsu Handotai Co., Ltd. 13-1, Isobe 2-chome Annaka-shi Gunma 379-0196 / JP | 02 /
YOSHIDA, Kazuhiko Nagano Denshi Co., Ltd. 1393, Yashiro Chikuma-shi Nagano 387-8555 / JP | [2009/27] | Representative(s) | Wibbelmann, Jobst Wuesthoff & Wuesthoff Patentanwälte und Rechtsanwalt PartG mbB Schweigerstrasse 2 81541 München / DE | [N/P] |
| Former [2009/27] | Wibbelmann, Jobst Wuesthoff & Wuesthoff Patent- und Rechtsanwälte Schweigerstrasse 2 81541 München / DE | Application number, filing date | 07827913.0 | 18.10.2007 | [2009/27] | WO2007JP01134 | Priority number, date | JP20060286080 | 20.10.2006 Original published format: JP 2006286080 | [2009/27] | Filing language | JA | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2008047478 | Date: | 24.04.2008 | Language: | JA | [2008/17] | Type: | A1 Application with search report | No.: | EP2075839 | Date: | 01.07.2009 | Language: | EN | [2009/27] | Type: | B1 Patent specification | No.: | EP2075839 | Date: | 11.05.2011 | Language: | EN | [2011/19] | Search report(s) | International search report - published on: | JP | 24.04.2008 | (Supplementary) European search report - dispatched on: | EP | 23.10.2009 | Classification | IPC: | H01L21/66, H01L23/544, // G01R31/26, H01L27/12 | [2010/51] | CPC: |
H01L22/14 (EP,US);
H01L22/00 (KR);
H01L27/1203 (EP,US);
H01L2924/0002 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
|
| Former IPC [2009/48] | H01L27/12, H01L21/66, H01L23/544, // G01R31/26 | ||
| Former IPC [2009/27] | H01L27/12, H01L21/66 | Designated contracting states | DE, FR [2010/48] |
| Former [2009/27] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | VERFAHREN ZUM EVALUIEREN EINES SOI-WAFERS | [2010/51] | English: | METHOD FOR EVALUATING SOI WAFER | [2010/51] | French: | PROCEDE D'EVALUATION D'UNE TRANCHE DE SOI | [2010/51] |
| Former [2009/27] | VERFAHREN ZUM EVALUIEREN EINES HALBLEITERWAFERS | ||
| Former [2009/27] | METHOD FOR EVALUATING SEMICONDUCTOR WAFER | ||
| Former [2009/27] | PROCEDE D'EVALUATION D'UNE TRANCHE DE SEMI-CONDUCTEUR | Entry into regional phase | 26.03.2009 | Translation filed | 26.03.2009 | National basic fee paid | 26.03.2009 | Search fee paid | 26.03.2009 | Designation fee(s) paid | 26.03.2009 | Examination fee paid | Examination procedure | 26.03.2009 | Examination requested [2009/27] | 21.05.2009 | Loss of particular rights, legal effect: designated state(s) | 30.06.2009 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR | 04.01.2010 | Amendment by applicant (claims and/or description) | 14.04.2010 | Despatch of a communication from the examining division (Time limit: M04) | 13.08.2010 | Reply to a communication from the examining division | 03.12.2010 | Communication of intention to grant the patent | 16.03.2011 | Fee for grant paid | 16.03.2011 | Fee for publishing/printing paid | Opposition(s) | 14.02.2012 | No opposition filed within time limit [2012/16] | Fees paid | Renewal fee | 19.10.2009 | Renewal fee patent year 03 | 19.10.2010 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [I] - ZAVRACKY P ET AL, "High quality SOI material produced using isolated silicon epitaxy", 19881003; 19881003 - 19881005, (19881003), page 21, XP010079150 [I] 1-3 * the whole document * | [A] - PELELLA M M ET AL, "A Novel Self-Aligned Substrate-Diode Structure for SOI Technologies", SOI CONFERENCE, 2005. PROCEEDINGS. 2005 IEEE INTERNATIONAL HONOLULU, HI, USA 03-06 OCT. 2005, PISCATAWAY, NJ, USA,IEEE, (20051003), ISBN 9780780392120, pages 169 - 170, XP010866602 [A] 1-3 * the whole document * DOI: http://dx.doi.org/10.1109/SOI.2005.1563576 | [A] - KUBOTA H; NAGANO H; SUGAMOTO J; MATSUSHITA H; MOMOSE M; NITTA S;SAMATA S; TSUCHIYA N, "Use of diode diagnostics for silicon wafer quality characterization;effect of COP on pn junction leakage", HIGH PURITY SILICON VI. PROCEEDINGS OF THE SIXTH INTERNATIONALSYMPOSIUM (ELECTROCHEMICAL SOCIETY PROCEEDINGS VOL. 2000-17) (SPIEVOL.4218)- 2000- ELECTROCHEM. SOC- PENNINGTON, NJ, USA, Pennington, NJ, USA, (2000), vol. 2000-17, ISBN 1566772842, pages 634 - 645 [A] 1-3 * page 634, line 1 - page 640, line 7; figures 1-9 * | [A] - AVSET B S, "Evaluation of silicon diodes made on a variety of high-resistivity phosphorus-doped substrates", NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH, SECTION - A:ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT, ELSEVIER, AMSTERDAM, NL, (19970111), vol. 385, no. 1, ISSN 0168-9002, pages 137 - 144, XP004034074 [A] 1-3 * the whole document * DOI: http://dx.doi.org/10.1016/S0168-9002(96)00882-0 | International search | [Y]JPH08255884 (MITSUBISHI MATERIALS CORP, et al); | [Y]JPH1154584 (SUMITOMO METAL IND) | Examination | - KUBOTA H. ET AL, "Use of diode diagnostics for silicon wafer quality characterization; effect of COP on pn junction leakage", HIGH PURITY SILICON VI : PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM, ELECTROCHEMICAL SOCIETY, US, (20000101), vol. 4218, ISBN 978-1-56677-284-6, pages 634 - 645, XP008113321 | by applicant | JP2001060676 | JP2001267384 | - "A Review of the Pseudo-MOS Transistor in SOI Wafers: Operation, Parameter Extraction, and Applications", S. CRISTOLEVEANU ET AL., IEEE Trans. Electron Dev, (2000), vol. 47, page 1018 | - H. J. HOVEL, "Si film electrical characterization in SOI substrates by HgFET technique", SOLID-STATE ELECTRONICS, (2003), vol. 47, doi:doi:10.1016/S0038-1101(03)00065-0, page 1311, XP004423934 DOI: http://dx.doi.org/10.1016/S0038-1101(03)00065-0 |