EP2112686 - Method for fabricating a dual workfunction semiconductor device made thereof [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.08.2012 Database last updated on 24.08.2024 | Most recent event Tooltip | 17.08.2012 | No opposition filed within time limit | published on 19.09.2012 [2012/38] | Applicant(s) | For all designated states IMEC Kapeldreef 75 3001 Leuven / BE | For all designated states Taiwan Semiconductor Manufacturing Co., Ltd. 8, Li-Hsin Road 6 300-077 HsinChu / TW | [2009/44] | Inventor(s) | 01 /
Yu, Hong Yu 50 Nanyang Avenue Block S2.2 Level B2, Room 45 639798 Singapore / SG | 02 /
Chang, Shou-Zen 12F, No. 1010-1, Sec.4 Jhongsing Road, Jhudong Township 310 Hsinchu Country / TW | 03 /
Hoffmann, Thomas Y. Kapucijnenvoer 114, 401 3000 Leuven / BE | 04 /
Absil, Philippe 208 Chaussee de Nivelles 1471 Loupoigne / BE | [2011/41] |
Former [2009/44] | 01 /
Yu, Hong Yu 50 Nanyang Avenue Block S2.2, Level B2, Room 45 639798 Singapore / SG | ||
02 /
Chang, Shou-Zen 12F, No. 1010-1, Sec.4 Jhongsing Road, Jhudong Township 310 Hsinchu Country / TW | |||
03 /
Hoffmann, Thomas Y. Kapucijnenvoer 114, 401 3000 Leuven / BE | |||
04 /
Absil, Philippe 208 Chaussee de Nivelles 1471 Loupoigne / BE | Representative(s) | Clerix, André IMEC vzw IP Department Kapeldreef 75 3001 Leuven / BE | [N/P] |
Former [2011/41] | Clerix, André IMEC vzw Kapeldreef 75 3001 Heverlee / BE | ||
Former [2009/44] | Clerix, André IMEC vzw Kapeldreef 75 B-3001 Heverlee / BE | Application number, filing date | 08075618.2 | 11.07.2008 | [2009/44] | Priority number, date | US20080046963P | 22.04.2008 Original published format: US 46963 P | [2009/44] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP2112686 | Date: | 28.10.2009 | Language: | EN | [2009/44] | Type: | A3 Search report | No.: | EP2112686 | Date: | 30.12.2009 | [2009/53] | Type: | B1 Patent specification | No.: | EP2112686 | Date: | 12.10.2011 | Language: | EN | [2011/41] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 01.12.2009 | Classification | IPC: | H01L21/8238, H01L21/324, H01L21/336, H01L29/49, H01L29/51, H01L21/268 | [2010/01] | CPC: |
H01L21/268 (EP,US);
H01L21/28176 (EP,US);
H01L21/324 (EP,US);
H01L21/823857 (EP,US);
H01L29/49 (EP,US);
H01L29/513 (EP,US);
|
Former IPC [2009/44] | H01L21/8238, H01L21/324, H01L21/336, H01L29/49, H01L29/51 | Designated contracting states | DE, FR, GB [2010/36] |
Former [2009/44] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR | Title | German: | Verfahren zur Herstellung eines Halbleiterbauelements mit dualer Austrittsarbeit-Funktion | [2009/44] | English: | Method for fabricating a dual workfunction semiconductor device made thereof | [2009/44] | French: | Procédé de fabrication d'un dispositif semiconducteur à double travail d'extraction et dispositif semiconducteur correspondant | [2009/44] | Examination procedure | 01.02.2010 | Examination requested [2010/11] | 12.03.2010 | Despatch of a communication from the examining division (Time limit: M04) | 03.06.2010 | Reply to a communication from the examining division | 01.07.2010 | Loss of particular rights, legal effect: designated state(s) | 06.08.2010 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR | 18.04.2011 | Communication of intention to grant the patent | 12.08.2011 | Fee for grant paid | 12.08.2011 | Fee for publishing/printing paid | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 12.03.2010 | Opposition(s) | 13.07.2012 | No opposition filed within time limit [2012/38] | Fees paid | Renewal fee | 29.07.2010 | Renewal fee patent year 03 | 29.07.2011 | Renewal fee patent year 04 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US2005045970 (ARIKADO TSUNETOSHI [JP], et al) [A] 1-16 * paragraph [0069]; figures 17a,17b * | [A] - SAMAVEDAM S B ET AL, "EVALUATION OF CANDIDATE METALS FOR DUAL-METAL GATE CMOS WITH HFO2 GATE DIELECTRIC", STRUCTURE AND MECHANICAL BEHAVIOR OF BIOLOGICAL MATERIALS. SYMPOSIUM - 29-31 MARCH 2005 - SAN FRANCISCO, CA, USA (IN: MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS),, (20020101), vol. 716, ISBN 978-1-55899-828-5, pages 85 - 90, XP009039269 [A] 1-16 * pages 85-89; figures 3,9 * | [A] - TRIYOSO D ET AL, "Evaluation of lanthanum based gate dielectrics deposited by atomic layer deposition", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AVS / AIP, MELVILLE, NEW YORK, NY, US, (20050125), vol. 23, no. 1, ISSN 1071-1023, pages 288 - 297, XP012079797 [A] 1-16 * pages 293-294; figures 11,13 * DOI: http://dx.doi.org/10.1116/1.1849217 | by applicant | - SCHAEFFER ET AL., J.VAC.SCI.TECHNOL. B, (2003), vol. 21, no. 1, pages 11 - 17 |