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EP2012566
European procedure
Extract from the Register of European Patents
EP About this file: EP2012566
| EP2012566 - Wired circuit board and producing method thereof [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 23.12.2011 Database last updated on 24.08.2024 | Most recent event Tooltip | 23.12.2011 | No opposition filed within time limit | published on 25.01.2012 [2012/04] | Applicant(s) | For all designated states Nitto Denko Corporation 1-1-2, Shimohozumi Ibaraki-shi Osaka 567-8680 / JP | [2009/02] | Inventor(s) | 01 /
Yokai, Takahiko c/o Nitto Denko Corporation 1-2, Shimo-hozumi 1-chome, Ibaraki-shi Osaka 567-8680 / JP | 02 /
Naito, Toshiki c/o Nitto Denko Corporation 1-2, Shimo-hozumi 1-chome Ibaraki-shi, Osaka 567-8680 / JP | [2011/17] |
| Former [2009/02] | 01 /
Yokai, Takahiko c/o Nitto Denko Corporation 1-2, Shimo-hozumi 1-chome, Ibaraki-shi Osaka 567-8680 / JP | ||
| 02 /
Naito, Toshiki Nitto Denko Corporation 1-2, Shimo-hozumi 1-chome Ibaraki-shi, Osaka 567-8680 / JP | Representative(s) | SSM Sandmair Patentanwälte Rechtsanwalt Partnerschaft mbB Joseph-Wild-Straße 20 81829 München / DE | [N/P] |
| Former [2009/02] | Schwabe - Sandmair - Marx Patentanwälte Stuntzstrasse 16 81677 München / DE | Application number, filing date | 08159609.0 | 03.07.2008 | [2009/02] | Priority number, date | JP20070177510 | 05.07.2007 Original published format: JP 2007177510 | [2009/02] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP2012566 | Date: | 07.01.2009 | Language: | EN | [2009/02] | Type: | A3 Search report | No.: | EP2012566 | Date: | 25.11.2009 | [2009/48] | Type: | B1 Patent specification | No.: | EP2012566 | Date: | 16.02.2011 | Language: | EN | [2011/07] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.10.2009 | Classification | IPC: | H05K1/05, H05K3/44 | [2009/02] | CPC: |
H05K1/05 (EP,US);
H05K1/056 (EP,US);
H05K3/44 (EP,US);
H05K2201/09745 (EP,US);
H05K2201/10416 (EP,US);
H05K2203/0323 (EP,US);
| Designated contracting states | DE, FR, GB [2010/30] |
| Former [2009/02] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR | Title | German: | Leiterplatte und Verfahren zu deren Herstellung | [2009/02] | English: | Wired circuit board and producing method thereof | [2009/02] | French: | Carte de circuit câblée et procédé de production correspondant | [2009/02] | Examination procedure | 07.05.2010 | Amendment by applicant (claims and/or description) | 11.05.2010 | Examination requested [2010/25] | 26.05.2010 | Loss of particular rights, legal effect: designated state(s) | 02.07.2010 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR | 04.11.2010 | Communication of intention to grant the patent | 29.12.2010 | Fee for grant paid | 29.12.2010 | Fee for publishing/printing paid | Opposition(s) | 17.11.2011 | No opposition filed within time limit [2012/04] | Fees paid | Renewal fee | 27.07.2010 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US2004252413 (NISHIYAMA NOBUMASA [JP]) [A] 1-6 * the whole document *; | [DA]JP2005011387 (HITACHI GLOBAL STORAGE TECH) [DA] 1-6 * abstract *; | [A]US2006199402 (ISHII JUN [JP], et al) [A] 3 * the whole document *; | [DA]JP2006245220 (NITTO DENKO CORP) [DA] 3 * abstract *; | [A]US2007017695 (ISHII JUN [JP], et al) [A] 1 * abstract *; | [A]US3424658 (NORTON CLYDE A) [A] 1,6 * the whole document * | by applicant | JP2005011387 | JP2006245220 |