EP2241167 - METHOD FOR ARRANGING VOLTAGE SUPPLY PLANES IN A PRINTED CIRCUIT BOARD TO WHICH IS ATTACHED A SEMICONDUCTOR DEVICE FOR REDUCTION OF JITTER AND PCB HAVING SUCH AN ARRANGEMENT [Right-click to bookmark this link] | |||
Former [2010/42] | REDUCTION OF JITTER IN A SEMICONDUCTOR DEVICE BY CONTROLLING PRINTED CIRCUIT BOARD OR PACKAGE SUBSTRATE STACKUP | ||
[2013/02] | Status | No opposition filed within time limit Status updated on 24.01.2014 Database last updated on 31.08.2024 | Most recent event Tooltip | 04.09.2015 | Lapse of the patent in a contracting state New state(s): MT | published on 07.10.2015 [2015/41] | Applicant(s) | For all designated states Xilinx, Inc. 2100 Logic Drive San Jose, California 95124 / US | [2010/42] | Inventor(s) | 01 /
DUONG, Anthony, T. 2100 Logic Drive San Jose, CA 95124 / US | [2010/42] | Representative(s) | Naismith, Robert Stewart, et al Marks & Clerk LLP Aurora 120 Bothwell Street Glasgow G2 7JS / GB | [2013/12] |
Former [2010/42] | Naismith, Robert Stewart, et al Marks & Clerk LLP Aurora 120 Bothwell Street Glasgow G2 7JS / GB | Application number, filing date | 08869756.0 | 05.11.2008 | [2010/42] | WO2008US82433 | Priority number, date | US20080008353 | 09.01.2008 Original published format: US 8353 | [2010/42] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2009088558 | Date: | 16.07.2009 | Language: | EN | [2009/29] | Type: | A1 Application with search report | No.: | EP2241167 | Date: | 20.10.2010 | Language: | EN | The application published by WIPO in one of the EPO official languages on 16.07.2009 takes the place of the publication of the European patent application. | [2010/42] | Type: | B1 Patent specification | No.: | EP2241167 | Date: | 20.03.2013 | Language: | EN | [2013/12] | Search report(s) | International search report - published on: | EP | 16.07.2009 | Classification | IPC: | H05K1/02 | [2010/42] | CPC: |
H05K1/0216 (EP,US);
H05K1/0262 (EP,US);
H01L2224/16 (EP,US);
H01L2924/15311 (EP,US);
H05K1/0298 (EP,US);
H05K2201/09327 (EP,US);
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR [2010/42] | Title | German: | VERFAHREN ZUM STAPELN VON SPANNUNGSVERSORGUNGSEBENEN IN EINER MIT EINER HALBLEITERVORRICHTUNG BESTÜCKTEN LEITERPLATTE ZUR JITTER-REDUKTION UND LEITERPLATTE MIT SOLCH EINEM STAPEL | [2013/02] | English: | METHOD FOR ARRANGING VOLTAGE SUPPLY PLANES IN A PRINTED CIRCUIT BOARD TO WHICH IS ATTACHED A SEMICONDUCTOR DEVICE FOR REDUCTION OF JITTER AND PCB HAVING SUCH AN ARRANGEMENT | [2013/02] | French: | MÉTHODE D'ARRANGEMENT DE PLANS D'ALIMENTATION EN TENSION DANS UNE CARTE À CIRCUIT IMPRIMÉ MUNIE D'UN DISPOSITIF À SEMI-CONDUCTEUR POUR LA RÉDUCTION D'INSTABILITÉS ET CIRCUIT IMPRIMÉ COMPRENANT UN TEL ARRANGEMENT | [2013/02] |
Former [2010/42] | JITTER-REDUKTION IN EINER HALBLEITERVORRICHTUNG DURCH STEUERUNG EINER BESTÜCKTEN LEITERPLATTE ODER EINES PAKETSUBSTRATSTAPELS | ||
Former [2010/42] | REDUCTION OF JITTER IN A SEMICONDUCTOR DEVICE BY CONTROLLING PRINTED CIRCUIT BOARD OR PACKAGE SUBSTRATE STACKUP | ||
Former [2010/42] | RÉDUCTION D'INSTABILITÉ DANS UN DISPOSITIF À SEMI-CONDUCTEUR PAR RÉGLAGE D'EMPILEMENT DE CARTES DE CIRCUIT IMPRIMÉ OU DE SUBSTRATS DE BOÎTIERS | Entry into regional phase | 30.04.2010 | National basic fee paid | 30.04.2010 | Designation fee(s) paid | 30.04.2010 | Examination fee paid | Examination procedure | 16.07.2009 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 30.04.2010 | Examination requested [2010/42] | 20.09.2010 | Amendment by applicant (claims and/or description) | 09.12.2010 | Despatch of a communication from the examining division (Time limit: M04) | 19.04.2011 | Reply to a communication from the examining division | 14.12.2012 | Communication of intention to grant the patent | 05.02.2013 | Fee for grant paid | 05.02.2013 | Fee for publishing/printing paid | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 09.12.2010 | Opposition(s) | 02.01.2014 | No opposition filed within time limit [2014/09] | Fees paid | Renewal fee | 24.11.2010 | Renewal fee patent year 03 | 23.11.2011 | Renewal fee patent year 04 | 26.11.2012 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | HU | 05.11.2008 | AT | 20.03.2013 | BE | 20.03.2013 | CY | 20.03.2013 | CZ | 20.03.2013 | DK | 20.03.2013 | EE | 20.03.2013 | FI | 20.03.2013 | HR | 20.03.2013 | IT | 20.03.2013 | LT | 20.03.2013 | LV | 20.03.2013 | MC | 20.03.2013 | MT | 20.03.2013 | NL | 20.03.2013 | PL | 20.03.2013 | RO | 20.03.2013 | SE | 20.03.2013 | SI | 20.03.2013 | SK | 20.03.2013 | TR | 20.03.2013 | BG | 20.06.2013 | NO | 20.06.2013 | GR | 21.06.2013 | ES | 01.07.2013 | IS | 20.07.2013 | PT | 22.07.2013 | LU | 05.11.2013 | CH | 30.11.2013 | LI | 30.11.2013 | [2015/41] |
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PT | 22.07.2013 | ||
CH | 30.11.2013 | ||
LI | 30.11.2013 | ||
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ES | 01.07.2013 | ||
IS | 20.07.2013 | ||
PT | 22.07.2013 | ||
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SI | 20.03.2013 | ||
BG | 20.06.2013 | ||
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ES | 01.07.2013 | ||
IS | 20.07.2013 | ||
PT | 22.07.2013 | ||
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ES | 01.07.2013 | ||
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SI | 20.03.2013 | ||
BG | 20.06.2013 | ||
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ES | 01.07.2013 | ||
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NO | 20.06.2013 | Cited in | International search | [XY]US6181004 (KOONTZ JERRY D [US], et al) [X] 1,2,6-9,13-15,18 * figures 3A,3B,4,7 * * column 4, line 58 - column 6, line 27 * * column 7, line 35 - line 49 * * column 10, line 26 - line 44 * [Y] 4,5,11,12; | [Y]US2005225955 (GREBENKEMPER JOHN [US], et al) [Y] 4,5,11,12 * figures 6-8 * * paragraphs [0002] , [0003] , [0005] , [0006] , [0046] - [0048] * |