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Extract from the Register of European Patents

EP About this file: EP2270964

EP2270964 - Method of controlling a power factor correction stage, a power factor correction stage and a controller therefor [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  14.07.2017
Database last updated on 14.09.2024
Most recent event   Tooltip06.03.2020Lapse of the patent in a contracting state
New state(s): TR		published on 08.04.2020  [2020/15]
Applicant(s)For all designated states
NXP B.V.
High Tech Campus 60
5656 AG Eindhoven / NL
[2011/01]
Inventor(s)01 / Groot, Humphrey de
c/o NXP Semiconductors
Betchworth House
Station Road
Redhill, Surrey UK RH1 1DL / GB
02 / Halberstadt, Hans
c/o NXP Semiconductors
Betchworth House
Station Road
Redhill, Surrey UK RH1 1DL / GB
 [2016/36]
Former [2011/01]01 / Groot, Humphrey de
c/o NXP Semiconductors Betchworth House Station Road
Redhill, Surrey UK RH1 1DL / GB
02 / Halberstadt, Hans
c/o NXP Semiconductors Betchworth House Station Road
Redhill, Surrey UK RH1 1DL / GB
Representative(s)Hardingham, Christopher Mark, et al
NXP Semiconductors
Intellectual Property Group
Abbey House
25 Clarendon Road
Redhill, Surrey RH1 1QZ / GB
[N/P]
Former [2016/36]Hardingham, Christopher Mark, et al
NXP B.V.
Intellectual Property & Licensing
Red Central
60 High Street
Redhill, Surrey RH1 1SH / GB
Former [2011/01]Hardingham, Christopher Mark, et al
NXP Semiconductors (UK) Ltd. Betchworth House 57-65 Station Road
Redhill, Surrey RH1 1DL / GB
Application number, filing date09008736.203.07.2009
[2011/01]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP2270964
Date:05.01.2011
Language:EN
[2011/01]
Type: B1 Patent specification 
No.:EP2270964
Date:07.09.2016
Language:EN
[2016/36]
Search report(s)(Supplementary) European search report - dispatched on:EP24.11.2009
ClassificationIPC:H02M1/42, H02M3/158
[2011/01]
CPC:
H02M1/0085 (EP,US); H02M1/4225 (EP,US); H02M3/1584 (EP,US);
H02M1/0032 (EP,US); H02M1/36 (EP,US); Y02B70/10 (EP,US);
Y02P80/10 (EP,US) (-)
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   SE,   SI,   SK,   SM,   TR [2016/36]
Former [2011/01]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  SE,  SI,  SK,  SM,  TR 
TitleGerman:Verfahren zur Steuerung einer Leistungsfaktorkorrekturstufe, Leistungsfaktorkorrekturstufe und Steuerung dafür[2011/01]
English:Method of controlling a power factor correction stage, a power factor correction stage and a controller therefor[2011/01]
French:Procédé de commande du circuit de correction du facteur de puissance, circuit de correction du facteur de puissance, et contrôleur associé[2011/01]
Examination procedure15.01.2010Amendment by applicant (claims and/or description)
05.07.2011Examination requested  [2011/32]
30.08.2013Despatch of a communication from the examining division (Time limit: M04)
16.12.2013Reply to a communication from the examining division
01.06.2016Communication of intention to grant the patent
19.07.2016Fee for grant paid
19.07.2016Fee for publishing/printing paid
19.07.2016Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  30.08.2013
Opposition(s)08.06.2017No opposition filed within time limit [2017/33]
Fees paidRenewal fee
01.08.2011Renewal fee patent year 03
31.07.2012Renewal fee patent year 04
31.07.2013Renewal fee patent year 05
31.07.2014Renewal fee patent year 06
31.07.2015Renewal fee patent year 07
01.08.2016Renewal fee patent year 08
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU03.07.2009
AT07.09.2016
BE07.09.2016
CY07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
MC07.09.2016
MK07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SI07.09.2016
SK07.09.2016
SM07.09.2016
TR07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
[2020/15]
Former [2019/52]HU03.07.2009
AT07.09.2016
BE07.09.2016
CY07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
MC07.09.2016
MK07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SI07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2019/46]HU03.07.2009
AT07.09.2016
BE07.09.2016
CY07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
MC07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SI07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2019/31]HU03.07.2009
AT07.09.2016
BE07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
MC07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SI07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2019/30]AT07.09.2016
BE07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
MC07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SI07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2017/37]AT07.09.2016
BE07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SI07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2017/34]AT07.09.2016
BE07.09.2016
CZ07.09.2016
DK07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2017/32]AT07.09.2016
BE07.09.2016
CZ07.09.2016
EE07.09.2016
ES07.09.2016
FI07.09.2016
HR07.09.2016
IT07.09.2016
LT07.09.2016
LV07.09.2016
NL07.09.2016
PL07.09.2016
RO07.09.2016
SE07.09.2016
SK07.09.2016
SM07.09.2016
BG07.12.2016
NO07.12.2016
GR08.12.2016
IS07.01.2017
PT09.01.2017
Former [2017/13]ES07.09.2016
FI07.09.2016
HR07.09.2016
LT07.09.2016
LV07.09.2016
NL07.09.2016
SE07.09.2016
NO07.12.2016
GR08.12.2016
Former [2017/11]ES07.09.2016
FI07.09.2016
HR07.09.2016
LT07.09.2016
SE07.09.2016
NO07.12.2016
GR08.12.2016
Former [2017/10]FI07.09.2016
HR07.09.2016
LT07.09.2016
SE07.09.2016
NO07.12.2016
Former [2017/09]FI07.09.2016
LT07.09.2016
NO07.12.2016
Former [2017/07]LT07.09.2016
Documents cited:Search[X]US2008316783  (O'LOUGHLIN MICHAEL J [US]) [X] 1,6,8 * paragraphs [0003] , [0004] , [0009] - [0011]; figure 1 * * paragraph [0018] - paragraph [0026] *;
 [X]  - JIUN-REN TSAI ET AL, "Interleaving Phase Shifters for Critical-Mode Boost PFC", IEEE TRANSACTIONS ON POWER ELECTRONICS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, (20080501), vol. 23, no. 3, ISSN 0885-8993, pages 1348 - 1357, XP011207868 [X] 1,6,8 * page 1355; figures 21,22 *
 [X]  - HUBER L ET AL, "Closed-Loop Control Methods for Interleaved DCM/CCM Boundary Boost PFC Converters", APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, 2009. APEC 2009. TWENTY-FOURTH ANNUAL IEEE, IEEE, PISCATAWAY, NJ, USA, (20090215), ISBN 978-1-4244-2811-3, pages 991 - 997, XP031442804 [X] 1,6,8 * page 991 *
 [X]  - T-F WU ET AL, "Integrated Circuits of a PFC Controller for Interleaved Critical-Mode Boost Converters", APPLIED POWER ELECTRONICS CONFERENCE, APEC 2007 - TWENTY SECOND ANNUAL IEEE, IEEE, PI, (20070201), ISBN 978-1-4244-0713-2, pages 1347 - 1350, XP031085385 [X] 1,6,8 * page 1347 - page 1348 *

DOI:   http://dx.doi.org/10.1109/APEX.2007.357690
 [A]  - SANGSUN KIM ET AL, "Control of multiple single phase PFC modules with a single low-cost DSP", APEC 2003. 18TH. ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION. MIAMI BEACH, FL, FEB. 9 - 13, 2003; [ANNUAL APPLIED POWER ELECTRONICS CONFERENCE], NEW YORK, NY : IEEE, US, (20030209), vol. 1, ISBN 978-0-7803-7768-4, pages 375 - 381, XP010631537 [A] 1-11 * page 378 *

DOI:   http://dx.doi.org/10.1109/APEC.2003.1179241
by applicantUS2008316783
    - "Interleaving Phase Shifters for Critical-Mode Boost PFC", JIUN-REN TSAI ET AL., IEEE TRANSACTIONS ON POWER ELECTRONICS, IEEE SERVICE CENTER, (20080501), vol. 23, pages 1348 - 1357
    - "Closed-Loop Coitrol Methods for Interleaved DCM/CCM Boundary Boost RFC Converters", HUBER L ET AL., APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, IEEE, (20090215), pages 991 - 997
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